ICs for Communications PCI Interface for Telephony/Data Applications PITA-2 PSB 4610 Version 2.2 Preliminary Data Sheet 01.00 DS 1 PSB 4610 Revision History: Current Version: 01.00 Previous Version: PSB 4610 Version 2.1 (12.99) Page Page (in previous (in current Version) Version) 181 Subjects (major changes since last revision) default value (40h) 1221 0001 changed to 1222 0001 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com A BM (R), A OP (R) , AR COFI (R) , ARC OFI(R) - BA , A RCOFI(R) -SP , Di giTa pe (R), EP IC (R)-1 , E PIC (R) - S, EL IC (R), FA LC (R)54 , FA LC (R) 56 , FA LC (R) -E1 , FA LC (R) -LH , IDEC (R), IO M (R) , IO M (R)-1, IOM (R)-2 , IPA T (R) - 2, IS AC (R)-P , ISA C (R) - S, IS AC (R)-S TE, ISA C (R) -P TE , ITAC (R), IWE (R) , MUSA C(R) -A, OCTA T (R) - P, QUA T(R) - S, SICAT (R), S ICOFI (R) , S ICO FI (R)-2 , S ICOFI (R) - 4, S ICO FI (R) - 4C , SL ICOFI(R) a re re gister ed tra de marks of Infine on Te chn olo gie s A G. A CE TM, AS MTM, AS PTM , PO TSW IRETM, Qu ad FALC TM, S COUT TM a re tra dem arks of In fine on Te ch no log ies A G. dition 0 1.00 Publishe d by Infine on Te chnologie s AG TR, Bala ns trae 73, 81 54 1 Munche n (c) Infine on Te chn olo gie s A G 2 000 Al l Ri gh ts Rese rved . Atte ntion ple as e! As far a s p aten ts or o ther r igh ts of thir d pa rties are conce rne d, lia bility is onl y a ssu me d fo r comp on ents, not for ap pli ca tion s, pr ocesse s a nd cir cu its i mple men ted with in comp on en ts or a ssemb lies. The i nform ation descri be s the type of co mpo ne nt an d shal l not be co nsid ere d as a ssu red ch ar acteri stics. Ter ms o f d elive ry and righ ts to cha ng e de sign r ese rved . Due to te ch nica l req uir eme nts co mpo ne nts may con ta in da ng ero us sub sta nce s. For in forma tion o n the type s i n qu estion ple ase con tact yo ur n ear est In fi neo n Tech no log ies Office. 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Critica l com pon en ts1 o f th e In fi ne on Te ch no log ies A G, ma y o nly b e used in li fe -sup po rt de vices or system s 2 with the e xp re ss wri tte n ap pro val of the Infin eon Techn olo gie s AG . 1 A critica l co mpo ne nt is a co mpo ne nt used i n a life- supp or t de vice or system wh ose fail ure ca n re ason ab ly b e exp ected to ca use the failu re of th at life -sup por t de vice o r system , or to a ffe ct its safety o r e ffe ctive ne ss of tha t de vice or system. 2 Life su ppo rt devi ce s o r syste ms a re i nten ded (a) to b e imp lan te d in the hum an b ody, or (b ) to sup por t a nd/o r mai ntain a nd su sta in h uma n life. If the y fail , it is r ea sona ble to a ssume th at th e he alth o f the u ser ma y b e en da ng ere d. PSB 4610 Organization of this Data Sheet * Chapter 1, Features Describes the general features of the PITA-2. * Chapter 2, Typical Applications with the PITA-2 Describes typical applications that can be realized with the PITA-2. * Chapter 3, Construction of the PITA-2 Shows a block diagram and describes the interfaces and their functions. * Chapter 4, Com munication with the PITA-2 Describes the PC I bus interface of the PITA-2. * Chapter 5, Com munication with External Components Gives a general description of the local bus interfaces of the PITA-2. * Chapter 6, Power Management Describes the power management functions (including D3cold) of the PITA-2. * Chapter 7, Reset and Interrupts Describes the requirements for reset and the behaviour of the PITA-2. * Chapter 8, Pinning Describes the pins, types of pins and the characteristics of the interfaces. * Chapter 9, Electrical Characteristics Describes electrical maximum ratings and electrical characteristics. * Chapter 10, Package Outlines Describes the package outlines. * Chapter 11, Configuration Space Register of the PITA -2 Contains descriptions of the C onfiguration Space Registers of the PITA-2. * Chapter 12, Internal Register of the PITA Contains descriptions of the Internal Registers of the PITA-2. * Chapter 13, Abbreviations Describes abbreviations occuring in this data sheet. * Chapter 14, Index Preliminary Data Sheet III 01.00 PSB 4610 Important Notes about this Data Sheet ________________________________________ What's New? The organization of the structure follows the guidelines of Information Mapping(R). ________________________________________ What is Information Mapping(R) ? This is a research based method for the - analysis - structure - presentation of user-orientated manuals. ________________________________________ Major Changes Instead of the used chapters with mono causal descriptions you now get - all information - for a scope - under the corresponding heading. ________________________________________ The Intention This Data Sheet is intended to be - - - - - easily surveyed increasingly readable customized applicable practice-orientated offering the quickest possible way to the required information. ________________________________________ Preliminary Data Sheet IV 01.00 PSB 4610 Table of Contents Page 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Typical Applications with the PITA-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Construction of the PITA -2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.3 Communication with the PITA-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Information about the PCI Configuration Space . . . . . . . . . . . . . . . . . . .12 Access to the PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Other Registers of the PCI Configuration Space . . . . . . . . . . . . . . . . . . . 20 PCI Master/Target Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Supported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Transaction Type Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Transaction Type Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Transaction Type Fast Back to Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt Control Register - Retry Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.3 Communication with External Com ponents . . . . . . . . . . . . . . . . . . . . . . 33 Serial DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Information about the DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Internal Registers of the D MA Controller . . . . . . . . . . . . . . . . . . . . . . . . . 41 IOM-2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 IOM-2 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 IOM-2 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 IOM-2 Modes - Supplementary Description . . . . . . . . . . . . . . . . . . . . . . . 56 Single Modem Mode V2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Single Modem Mode ALIS V3.X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Dual Modem/Modem+Voice Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 ALE after System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 ALE after internal Softw are Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ALE after setting the Parallel Interface Mode Bit . . . . . . . . . . . . . . . . . . . 83 Non Multiplexed Mode (Write Transaction) . . . . . . . . . . . . . . . . . . . . . . . 84 Non Multiplexed Mode (Read Transaction) . . . . . . . . . . . . . . . . . . . . . . . 86 Multiplexed Mode (Write Transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Multiplexed Mode (Read Transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Transaction Disconnect with Target Abort . . . . . . . . . . . . . . . . . . . . . . . . 89 Transaction Termination w ith Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Timing of the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 General Purpose I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Semiconductor Group V Preliminary Data Sheet 01.00 PSB 4610 Table of Contents Page 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.4 5.4.1 5.4.2 5.4.3 Information about the GP I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . .98 Timing of the GP I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Internal Registers of the GP I/O Interface . . . . . . . . . . . . . . . . . . . . . . .101 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Usage of the GP I/O Interface as ALIS V2.1 Control Interface . . . . . . .113 SPI EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Information about the SPI EEPROM Interface . . . . . . . . . . . . . . . . . . .116 Timing of the SPI EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . .119 Internal Registers for the SPI EEPROM Interface . . . . . . . . . . . . . . . . . 121 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 Power Managem ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Information about the Power Supply Concept . . . . . . . . . . . . . . . . . . . . . . 124 Information about the Power Management States . . . . . . . . . . . . . . . .126 Considerations about Power Consumption and Reporting . . . . . . . . . .128 Configuration Space Registers of the Power Management . . . . . . . . . .131 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Design Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Compatibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7 7.1 7.2 Reset and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 8 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 9 9.1 9.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11 11.1 11.2 11.3 Configuration Space Register of the PITA-2 . . . . . . . . . . . . . . . . . . . . . 173 Description of the Register Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Registers which do not occur elsew here in the D ata Sheet . . . . . . . . . . .185 12 12.1 12.2 12.3 Internal Register of the PITA . . . . . . . . . . . . . . . . . . . . . . Description of the Register Types . . . . . . . . . . . . . . . . . . . . Internal Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers which do not occur elsew here in the D ata Sheet 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Semiconductor Group VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 .194 .195 .202 Preliminary Data Sheet 01.00 PSB 4610 Introduction ________________________________________ What is the PITA-2? The PITA-2 is a cost-effective PCI bridge for industrial and communication applications. It supports dual cards and D3cold power management. ________________________________________ The PITA-2 can be used in * PC I ISDN cards. * PC I hardware modems. * PC I software modems. * Industrial PCI bridge applications. ________________________________________ Interfaces of the PITA-2 The PITA-2 offers the following interfaces: Interfaces to find in PCI Master/Target Controller see chapter 4.2 on page 22 Serial DMA Interface see chapter 5.1 on page 34 Parallel Interface see chapter 5.2 on page 78 Preliminary Data Sheet 1 01.00 PSB 4610 The PITA-2 offers the following interfaces: Interfaces to find in General Purpose I/O Interface see chapter 5.3 on page 97 SPI EEPROM Interface see chapter 5.4 on page 115 Preliminary Data Sheet 2 01.00 PSB 4610 Features 1 Features ________________________________________ Compliant with * PC 99 (PCI requirements) * PC I Bus Specification Version 2.2 * PC I Power Management Specification Version 1.1 ________________________________________ Highlights * Dual Card support (3.3V and 5V signaling environment) * Extensive Pow er Management Features (including D3cold) * Automatic C onfiguration with Customer Specific Values ________________________________________ Interfaces * PC I Master Target Interface - PC I 2.2 compliant - 32 bit - 33 MHz * Serial Interface - Supports IOM-2 Modes - Supports serial interface to the ALIS chip-set family - DMA Controller for serial communication - 16 word FIFOs for each direction * Parallel Interface with chip select logic supporting up to three external components * General Purpose I/O Interface with interrupt capability * SPITM Interface for optional EEPROM ________________________________________ Preliminary Data Sheet 3 01.00 PSB 4610 Features ________________________________________ Compatibility * ALIS V2.1 PSB 4596 * ALIS V3.X PSB 4596 * ISDN IOM-2 Components, e.g.: - IEC-Q family - SBCX, SBCX-X * Components consisting of a parallel multiplexed or non multiplexed Intel/ Infineon Interface, e.g: - IPAC, IPAC-X - ISAC-S, ISAC-SX, ISAC-SX TE ________________________________________ Preliminary Data Sheet 4 01.00 PSB 4610 Typical Applications with the PITA-2 2 Typical Applications with the PITA-2 ________________________________________ Overview Besides all the applications that require only a simple PCI interface there are some applications which the PITA-2 is especially suited for. Simple applications benefit from the easy configuration of the PITA-2, the extensive power management support and the standard interfaces on the local bus side. Telecommunication applications (e.g modems) benefit from the integrated master DMA controller as w ell as the IOM-2/GCI bus interface. This allow s for easy connection of most telecommunications transceivers and substantially reduces the CPU workload. Furthermore the PITA-2 fully supports D3cold state. This allows the PC to enter a deep sleep state and still be able to react to an incoming call at the same time. ________________________________________ ISDN-S Interface Application with the IPAC PSB 2115 IPAC S0-Interface uC Interface SPI EEPROM PSB 4610 PTA-2 PCI Bus Preliminary Data Sheet 5 01.00 PSB 4610 Typical Applications with the PITA-2 ________________________________________ ISDN-U Interface Application with the 3PAC and IEC-Q TE PSB 2113 3PAC PSB21911 IEC-Q TE U-In terface uC Interface SPI PSB 4610 PTA-2 EEPROM PCI Bus ________________________________________ Preliminary Data Sheet 6 01.00 PSB 4610 Construction of the PITA-2 3 Construction of the PITA-2 ________________________________________ Overview The PITA-2 provides a Peripheral Component Interconnect (PCI) bus interface which acts as a bridge between the PCI bus and the different controllers and interfaces: * The Parallel Interface Control supports up to three external devices. * The Serial Interface is controlled by the internal D MA Controller; serial communication uses transmit and receive FIFOs. * The EEPROM for configuration of the PITA-2 and customer specific data storage. * The General Purpose I/O Interface. ________________________________________ Block Diagram of the PITA-2 PCI-Bus PCI Controller DMA Controller TX FIFO RX FIFO PITA-2 EEPROM Control SPIInterface Parallel Interface Control Parallel Microcontroller Interface Serial Interface Control Serial Interface General Purpose Interface ________________________________________ Preliminary Data Sheet 7 01.00 PSB 4610 Construction of the PITA-2 ________________________________________ Description of the single Blocks N ame provides supports PCI Bus C ontrol * a 32 bit interface at speeds up to 33 MHz * Bus Master DMA capability for data passing through the Serial Interface * Target capability for data passing through the Parallel Interface * * * * D0 D1 D2 D3hot and D3cold * 5V environment * 3.3V environment * Vaux supply Parallel Interface C ontrol Chips with a Infineon/ Intel Standard Parallel Interface, including: * ISDN devices * Modems DSPs * Industrial devices Serial Interface C ontrol Preliminary Data Sheet Notes Chips with a serial interface, including: * Analog voice codecs * Analog modem codecs * IOM-2 devices. 8 Three predecoded chip select lines Can be used for pinstrapping the subsystem/ subsystem vendor ID Transmit and receive data are held in separate 16 word FIFOs. 01.00 PSB 4610 Construction of the PITA-2 Description of the single Blocks (cont'd) N ame provides supports Notes EEPROM C ontrol * additional information, such as - the Subsystem ID All EEPROMs with SPI interface This is an optional feature that can be used to customize the PITA-2 configuration at start up. - the Subsystem Vendor ID - extensive power management information General Purpose I/O Interface * GP outputs * GP inputs * GP interrupt inputs It can configured act as be to * Input pins * Output pins * Interrupt pins. Can be used for pinstrapping the subsystem ID ________________________________________ Preliminary Data Sheet 9 01.00 PSB 4610 Communication with the PITA-2 4 Communication with the PITA-2 ________________________________________ For communication with the PITA-2 the following blocks are used: C omponents Page PCI Configuration Space 11 PCI Master/Target Controller 22 Interrupt Control Register - Retry C ounter 31 ________________________________________ Preliminary Data Sheet 10 01.00 PSB 4610 Communication with the PITA-2 4.1 PCI Configuration Space ________________________________________ Overview Overview Page Information about the PCI Configuration Space 12 Access to the PCI Configuration Space 15 Base Address Register 16 Other Registers of the PCI C onfiguration Space 20 ________________________________________ Preliminary Data Sheet 11 01.00 PSB 4610 Communication with the PITA-2 4.1.1 Information about the PCI Configuration Space ________________________________________ Description The PCI Configuration Space contains information about * the PCI device * the requested address space in the memory space of the PC I system. The address space includes 64 32-bit registers w here the first 16 registers build the configuration space header (00h-3Ch, refer to "Configuration Space Register of the PITA-2" on page 173) ________________________________________ Preliminary Data Sheet 12 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Construction of the PCI Configuration Space 31 24 23 16 15 8 7 0 D evice ID Vendor ID 00h Status Com mand 04h Class Code BIST Header Type Latency Timer Revision ID 08h Cach Line Size 0Ch Base Address Register 0 (Internal Registers) 10h Base Address Register 1 (Parallel Interface) 14h Base Address Register 2 (unused) 18h Base Address Register 3 (unused) 1Ch Base Address Register 4 (unused) 20h Base Address Register 5 (unused) 24h CardBus CIS Pointer 28h Subsystem ID Subsystem Vendor ID Expansion ROM Base Address 30h Reserved Cap_Ptr Reserved Max_Lat Min_Gnt Power Management Capabilities Data 2Ch 34h 38h Interrupt Pin Interrupt Line 3Ch Next Item Pointer Capability ID 40h Bridge Support PMCSR 44h Power Data Register 1 48h Power Data Register 2 4Ch Power Data Register 3 50h Unused Configuration Space Registers 54h CardBus C IS 58h 5Ch Unused Configuration Space Registers shaded fields loaded during initialization if EEPROM is connected Preliminary Data Sheet 13 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Description of Register Types Type Description PE H * read only via PC I * these bits are initialized by pinstrapping during PCI reset or by the optional EEPR OM * read only via PC I * hardwired RC * read clear via PCI * these bits are set by the internal logic * these bits can be read out and reset by writing logical "1" to them * writing logical "0" doesn't influence the states of these bits RW * read write via PCI * these bits can be read out and written via the PCI bus E * read only via PC I * these bits are initialized to a default value during PCI reset or by the optional EEPROM ________________________________________ Preliminary Data Sheet 14 01.00 PSB 4610 Communication with the PITA-2 4.1.2 Access to the PCI Configuration Space ________________________________________ Description The PITA-2 supports single 32 bit data transactions for the access to the PCI Configuration Space. ________________________________________ Special Qualities N ame Description Subsystem ID * lower 4 bits can be set via pinstrapping if no EEPROM is used * with external EEPROM the complete 16 bit value can be loaded for the Subsystem ID Subsystem Vendor ID * 16 bit ID of the card manufacturer * has to be applied for at the PCI Special Interest Group * can be set via pinstrapping during reset if no EEPROM is used * can be loaded from external EEPROM C ardBus CIS Pointer is not supported by the PITA-2, although it is implemented in the PCI Configuration Space ________________________________________ Preliminary Data Sheet 15 01.00 PSB 4610 Communication with the PITA-2 4.1.3 Base Address Register ________________________________________ Base Address Registers 0 - 5 B ase Address Register Description Base Address Register 0 * the lower 12 bits are hardwired to "0" * occupies an address space of 4K * allows access to the internal registers of the PITA-2 Base Address Register 1 * the lower 12 bits are hardwired to "0" * allows continuous read and write operations for access to the parallel interface * occupies an address space of 4K * address space is logically segmented in 4x1K address blocks Base Address Register 2 - 5 not used ________________________________________ Structure of the Address Space of Base Address Register 1 A ddress Space Access to 3FFh - 000h device 1 on the parallel interface (CS0) 7FFh - 400h device 2 on the parallel interface (CS1) BFFh - 800h device 3 on the parallel interface (CS2) FFFh - C00h not used ________________________________________ Preliminary Data Sheet 16 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Configuration Space Register: 04h B it 1 Memory_Access_Enable Type RW D efault Value 0b D escription Only if this bit is set to `1', the PCI interface will react on transactions to the base address registers BAR (all Base Address Registers are defined as memory mapped). ________________________________________ Configuration Space Register: 10h B it 31:12 Base Address Register 0 Type RW D efault Value 0000h B it 11:00 Base Address Register 0 Type H Value 000h D escription BAR0 contains the base address of an address space in the PCI main memory through which the internal registers of the PITA-2 can be accessed. ________________________________________ Preliminary Data Sheet 17 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Configuration Space Register: 14h B it 31:12 Base Address Register 1 Type RW D efault Value 0000h B it 11:00 Base Address Register 1 Type H Value 000h D escription BAR1 contains the base address of a 4-kilobyte address space in the PCI main memory through which the parallel micro controller interface of the PITA-2 can be accessed. ________________________________________ Configuration Space Register: 18h B it 31:0 Base Address Register 2 Type H Value 0000 0000h D escription Base Address Register 2 is not supported. ________________________________________ Configuration Space Register: 1Ch B it 31:0 Base Address Register 3 Type H Value 0000 0000h D escription Base Address Register 3 is not supported. Preliminary Data Sheet 18 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Configuration Space Register: 20h B it 31:0 Base Address Register 4 Type H Value 0000 0000h D escription Base Address Register 4 is not supported. ________________________________________ Configuration Space Register: 24h B it 31:0 Base Address Register 5 Type H Value 0000 0000h D escription Base Address Register 5 is not supported. ________________________________________ Preliminary Data Sheet 19 01.00 PSB 4610 Communication with the PITA-2 4.1.4 Other Registers of the PCI Configuration Space ________________________________________ Configuration Space Register: 28h B it 31:0 CardBus CIS Pointer Type H Value 0000 002C0h D escription Unused B it 31:28 ROM_Image_Number Type H Value 0000b D escription Unused B it 27:3 Address_Space_Offset Type H Value 000054h D escription Unused B it 2:0 Address_Space_Indicator Type H Value 000b D escription Unused ________________________________________ Preliminary Data Sheet 20 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Note The CardBus function is not supported in this version of the PITA-2. ________________________________________ Configuration Space Register: 2Ch B it 31:20 Subsystem ID Type E D efault Value 000h B it 19:16 Subsystem ID Type PE Value Pinstrap value or EEPROM value D escription Identifies a specific board of a manufacturer on which the PITA-2 is used. The 4 LSBs will be set by pinstrapping GP0-3 during PCI reset if no EEPROM is used and the complete 16 bit register can be loaded if the optional EEPROM is used. B it 15:0 Subsystem Vendor ID Type PE Value Pinstrap value or EEPROM value D escription Marks of the Vendor of the board on which the PITA-2 is used. This register will be set by pinstrapping PAD0-7 and PA0-7 during PCI reset if no EEPROM is used or configured from a connected EEPROM. This ID is allocated by the PCI SIG. ________________________________________ Preliminary Data Sheet 21 01.00 PSB 4610 Communication with the PITA-2 4.2 PCI Master/Target Controller ________________________________________ Introduction The interface of the PCI bus is represented by the PCI Master/Target C ontroller. This controller is part of the PITA-2. The PCI Master/Target C ontroller supports * several types of transactions, * Base Address Registers 0 and 1. The PCI Master/Target C ontroller * has a "Medium Device Select" behavior, * truncates burst transactions at the end of the first dataphase. ________________________________________ Preliminary Data Sheet 22 01.00 PSB 4610 Communication with the PITA-2 4.2.1 Supported PCI Commands ________________________________________ PCI Master Controller: PCI Command Transaction Type Memory Read single transfer Memory Write single transfer ________________________________________ PCI Target Controller: PCI Command Transaction Type Memory Read single transfer Memory Read Multiple mapped on Memory Read Memory Read Line mapped on Memory Read Memory Write single transfer Memory Write and Invalidate mapped on Memory Write C onfiguration Read single transfer C onfiguration Write single transfer ________________________________________ Preliminary Data Sheet 23 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Overview Overview Page Transaction Type Burst Read 25 Transaction Type Burst Write 27 Transaction Type Fast Back to Back 29 ________________________________________ Note The following timing diagrams are meant as an example and show transactions to and from the PCI configuration space. ________________________________________ Preliminary Data Sheet 24 01.00 PSB 4610 Communication with the PITA-2 4.2.2 Transaction Type Burst Read ________________________________________ Description * Asserting IR DY and STOP at the first dataphase leads to the disconnection (Disconnect-B) of the burst read transaction by the PITA-2. * STOP is asserted until FRAME is deasserted. * Deassertion of FRAME means that STOP and DEVSEL together are deasserted. ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 IDSEL FRAME IRDY TRDY DEVSEL AD31-0 ADR C/BE3-0 1010b DATA BE STOP ________________________________________ Preliminary Data Sheet 25 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Configuration Space Register: 04h B it 26:25 DEVSEL_Timing Type H Value 01b D escription `01' = medium timing, i.e. the DEVSEL signal will be asserted from the PCI interface with the second positive PCI clock edge after FRAME was asserted on the PCI bus by a master. ________________________________________ Preliminary Data Sheet 26 01.00 PSB 4610 Communication with the PITA-2 4.2.3 Transaction Type Burst Write ________________________________________ Description * Asserting IR DY and STOP at the first dataphase leads to the disconnection (Disconnect-B) of the burst write transaction by the PITA-2. * STOP is asserted until FRAME is deasserted. * Deassertion of FRAME means that STOP and DEVSEL together are deasserted. ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 IDSEL FRAME IRDY TRDY DEVSEL AD31-0 ADR DATA1 DATA2 C/BE3-0 1010b BE1 BE2 STOP ________________________________________ Preliminary Data Sheet 27 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Configuration Space Register: 04h B it 26:25 DEVSEL_Timing Type H Value 01b D escription `01' = medium timing, i.e. the DEVSEL signal will be asserted from the PCI interface with the second positive PCI clock edge after FRAME was asserted on the PCI bus by a master. ________________________________________ Preliminary Data Sheet 28 01.00 PSB 4610 Communication with the PITA-2 4.2.4 Transaction Type Fast Back to Back ________________________________________ Description With the fast back to back transaction a PCI Master Controller can perform * several write transactions * a read transaction as last transaction without setting the PCI bus to IDLE state in between or releasing the bus to another master. At the end of a transaction: * The Master asserts the FRAME signal and at the same time the TRDY signal is deasserted. The transaction is answered with a RETRY signal by the PITA-2 * if the parallel interface is included in the fast back to back transaction * and the parallel interface is still busy. ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 IDSEL FRAME IRDY TRDY DEVSEL AD31-0 ADR DATA1 ADR2 DATA2 C/BE3-0 1011b BE1 1011b BE2 STOP ________________________________________ Preliminary Data Sheet 29 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Configuration Space Register: 04h B it 23 Fast_Back_To_Back_Capability Type H Value 1b D escription The PITA-2 supports fast back-to-back. B it 9 Fast_Back_To_Back_Enable Type H Value 0b D escription The PITA-2 itself generates no fast back-to-back transactions. ________________________________________ Preliminary Data Sheet 30 01.00 PSB 4610 Communication with the PITA-2 4.3 Interrupt Control Register - Retry Counter ________________________________________ Description * Part of the PCI Master Target Controller * Functionality: 1. Disconnection of the PCI Master transaction with Retry by the addressed PCI Slave. 2. Decrement of the counter. 3. The Retry_Counter_Int bit is set. 4. An interrupt will be generated if the Retry_Counter_Enable bit is set. 5. The PCI Master starts the transaction again. ________________________________________ Internal Register: 00h B it 27 RETRY_C ounter_Down_Int_En Type RW D efault Value 0b D escription Enable for the Retry_Counter_Down interrupt bit B it 11 Retry_Counter_Int Type RC D efault Value 0b D escription If a PCI Master initiated transaction is retried from a PC I Slave with the number of retries defined in the Retry_Counter register, this interrupt bit is set by the PCI interface. ________________________________________ Preliminary Data Sheet 31 01.00 PSB 4610 Communication with the PITA-2 ________________________________________ Internal Register:1Ch B it 23:16 Retry C ount R egister Type RW D efault Value 00h D escription Hold the number of retries for a single PCI master transaction before the PITA-2 will assert an interrupt (if enabled). As an example, if this register is programmed w ith the value 4, the PITA-2 w ill retry a single PCI transaction up to four times as a master before it asserts an interrupt. The PITA-2 will continue to retry the transaction until it succeeds or the software decides to abort the whole transaction. ________________________________________ Preliminary Data Sheet 32 01.00 PSB 4610 Communication with External Com ponents 5 Communication with External Components ________________________________________ Introduction This chapter describes the interfaces for communication with devices on the local bus side (i.e. not the PCI bus side). ________________________________________ Interfaces Interfaces Page Serial DMA Interface 34 Parallel Interface 78 General Purpose I/O Interface 97 SPI EEPROM Interface 115 ________________________________________ Preliminary Data Sheet 33 01.00 PSB 4610 Communication with External Com ponents 5.1 Serial DMA Interface ________________________________________ Introduction The serial D MA interface is used in different modes to transmit and receive 16 bit/ 32 bit data frames. These data frames have different content and structures: * * * * Data Data/Voice and Command Data/Voice and Command for two codecs Different time slots on IOM-2. ________________________________________ Usage of the Serial DMA Interface The serial DMA interface is clocked by default with the internally generated clock (DCL = PCI clock divided by 40). The Ser_Clock_Set bit must be set in the Serial Clock Select register to '1' w hen the interface shall work in ALIS V3.X or IOM-2 mode Resetting this bit can result in an unknown behavior of the FIFOs and the serial controller. The serial DMA interface is fully controlled by the DMA controller. ________________________________________ Preliminary Data Sheet 34 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Overview Overview Page D MA Controller 36 IOM-2 Mode 1 47 IOM-2 Mode 2 50 IOM-2 Mode 3 53 IOM-2 Modes - Supplementary Description 56 Single Modem Mode V2.1 61 Single Modem Mode ALIS V3.X 65 D ual Modem/Modem+Voice Mode 73 Loop Back Mode 76 ________________________________________ Preliminary Data Sheet 35 01.00 PSB 4610 Communication with External Com ponents 5.1.1 DMA Controller ________________________________________ Overview Overview Page Information about the DMA Controller 37 Internal Registers of the DMA Controller 41 ________________________________________ Preliminary Data Sheet 36 01.00 PSB 4610 Communication with External Com ponents 5.1.2 Information about the DMA Controller ________________________________________ Description For the control of the DMA Controller, three register are implemented in the internal registers: * The Circular Buffer Start Address is a 4-kbyte aligned PCI address w hich points to a 4-kbyte circular buffer in the PCI main memory. All DMA read/write transactions between host and PITA will be processed via this 4-kbyte address space. * The DMA Control register includes the 6-bit parameter DMA Select which is used to define the mode for the next DMA transfer. With the DMA_Start bit the DMA transfer can be started and stopped. * The contents of the DMA Write Count Register is interpreted as a threshold for the write transfers from the DMA controller. ________________________________________ Function of the DMA Controller Phase Function 1 DMA_Start bit is set in the DMA Control Register and a DMA transfer is started as defined in the DMA Select Register. 2 The DMA controller loads the Circular Buffer Start Address to its Actual Circular Buffer Pointer. 3 The DMA controller fills the TX FIFO by reading 15 times through the PCI interface (PCI master mode) from the circular buffer. 4 The DMA controller signals the end of the initial sequence. 5 The DMA controller increments the Actual Circular Buffer Pointer by 4 each read transfer. 6 The DMA controller loads the contents of the 12 bit DMA Write Count R egister to its internal 12 bit DMA write counter. 7 After the first 15 read transfers in the beginning of the 16th read transfer the DMA controller starts the normal D MA algorithm. ________________________________________ Preliminary Data Sheet 37 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Function of the DMA Algorithm Phase Function 1 The D MA controller reads the 16th data word from the current address in the circular buffer (Actual Circular Buffer Pointer) to the internal TX FIFO. 2 The D MA controller writes the first received 16-bit data word from the RX FIFO to the same address in the circular buffer. 3 The D MA controller increments the Actual Buffer Pointer by 4. 4 The D MA controller reads the 17th data word from the current address in the circular buffer (Actual Circular Buffer Pointer) to the internal TX FIFO. 5 The D MA controller writes the second received 16-bit data word from the RX FIFO to the same address in the circular buffer. 6 The D MA controller increments the Actual Buffer Pointer by 4. 7 and so on ________________________________________ DMA Write Counter After each write transaction from the RX FIFO to the buffer the internal DMA write counter is incremented by 1. If this counter reaches '0' an interrupt is generated and the counter is loaded again with the contents of the DMA Write Counter Register. The internal DMA write counter is decremented every two write transactions as long as two 16 bit values per FSC frame are transferred in the following modes: * * * * 32 bit frame mode dual modem mode modem+voice mode IOM-2 mode 2 and 3. ________________________________________ Preliminary Data Sheet 38 01.00 PSB 4610 Communication with External Com ponents ________________________________________ DMA_Start bit * The reset of the DMA_Start bit stops the DMA transfer immediately. * The assertion of the DMA_Start bit resets the TX and RX FIFO's. This means that all FIFO data is lost when the D MA transfer is stopped. ________________________________________ Data in the Circular Buffer Since no data is written from the R X FIFO to the circular buffer for the first 15 addresses, the first interrupt after the DMA_Start assertion means that the received data is available in the circular buffer on address * 003Ch to 003Ch + [D MA Write Count]: 16 bit frame modes * 003Ch to 0003Ch + 2 x [DMA Write Count]: 32 bit frame modes. During normal data transfer every interrupt means that received data is available in the circular buffer on address * [end address from last interrupt] to [end address from last interrupt] + [DMA Write Count]: 16 bit frame modes * [end address from last interrupt] to [end address from last interrupt] + 2 x [DMA Write Count]: 32 bit frame modes ________________________________________ Preliminary Data Sheet 39 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Example for DMA controlled Data Transfer via Circular Buffer The status of the DMA controller: 16 bit frame access mode (ALIS V2.1 mode/IOM-2 mode 1) when three data frames are already written to the TX line. Circular Buffer Memory 31 0000h 0004h 0008h 0038h 003Ch 16 15 Serial Control 0 don't care don't care don't care don't care don't care TX data 1 TX data 2 TX data 3 TX data 4 TX data 5 TX data 4 TX data 5 TX data 6 TX data 7 TX data 8 RX data 20 RX data 19 RX data 18 RX data 17 RX data 16 don't care don't care don't care don't care don't care don't care don't care TX data 6 TX data 7 TX data 8 TX data 9 TX data 10 TX data 11 TX data 12 TX data 9 TX data 10 TX data 11 TX data 12 TX data 13 TX data 14 TX data 15 RX data 15 RX data 14 RX data 13 RX data 12 RX data 11 RX data 10 RX data 9 don't care don't care don't care don't care don't care don't care don't care TX data 13 TX data 14 TX data 15 RX data 1 RX data 2 RX data 3 RX data 4 TX data 16 TX data 17 TX data 18 TX data 19 RX data 8 RX data 7 RX data 6 RX data 5 don't care don't care don't care don't care TX data 20 TX data 21 TX data 22 TX data 23 TX FIFO Actual_Circular_Buffer_Pointer RX FIFO DMA Controller PITA ________________________________________ Preliminary Data Sheet 40 01.00 PSB 4610 Communication with External Com ponents 5.1.3 Internal Registers of the DMA Controller ________________________________________ Internal Registers: 00h B it 26 FIFO_Overflow_Empty_Int_En Type RW D efault Value 0b D escription Enable for the FIFO_Overflow_Empty interrupt bit B it 25 DMA_Write_Counter_Overflow _Int_En Type RW D efault Value 0b D escription Enable for the DMA_Write_Counter_Overflow interrupt bit. B it 24 DMA_Write_Counter_Int_En Type RW D efault Value 0b D escription Enable for the DMA_Write_Counter interrupt bit. B it 10 FIFO_Overflow_Empty_Int Type RC D efault Value 0b D escription During a DMA transfer the serial controller was unable to write received data to the RX FIFO because is was already full or the serial controller was unable to send data after the rising FSC edge because of empty TX FIFO. Preliminary Data Sheet 41 01.00 PSB 4610 Communication with External Com ponents Internal Registers: 00h (cont'd) B it 9 DMA_Write_Counter_Overflow _Int Type RC D efault Value 0b D escription This bit is set if the internal DMA write counter is counted down w hile the DMA_Write_Counter_Int bit is still active. This means that the interrupt generated by the DMA_Write_Counter_Int bit is not yet processed. B it 8 DMA_Write_Counter_Int Type RC D efault Value 0b D escription This bit is set if the number of data, defined in the D MA Write Count Register is written through the PCI interface. In the 32-bit modes (dual modem, modem+voice, IOM-2 mode 2, IOM-2 mode 3) this bit is set if the number of data pairs defined in the DMA Write Count Register is transferred through the PCI interface. ________________________________________ Preliminary Data Sheet 42 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Registers: 04h B it 31:0 DMA Control Register B it 31:9 Reserved Type H Value 0000000h D escription Reserved B it 8 DMA_Start Type RW D efault Value 0b D escription By asserting this bit a DMA transfer between the circular buffer and the serial DMA interface using internal RX/TX FIFOs is started. This bit is reset by the host if the DMA transfer is to be finished. B it 7:6 Reserved Type H Value 00b D escription Reserved Preliminary Data Sheet 43 01.00 PSB 4610 Communication with External Com ponents Internal Registers: 04h (cont'd) B it 5:0 DMA Select Type RW D efault Value 000000b D escription Used to define the mode for the next DMA transfer: - Mode 1 ('000001'): - Mode 2 ('000010'): - Mode 3 ('000100'): V3.X - Mode 4 ('001000'): - Mode 5 ('010000'): - Mode 6 ('100000'): Single Modem Mode V2.1 Single Modem Mode V3.X Dual Modem/Modem+Voice Mode IOM-2 Mode 1 IOM-2 Mode 2 IOM-2 Mode 3 With the DMA_Start bit the DMA transfer can be started or stopped. ________________________________________ Preliminary Data Sheet 44 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Registers: 08h B it 31:12 Circular Buffer Start Address Type RW D efault Value 000000h B it 11:0 Circular Buffer Start Address Type H Value 000h D escription * 4-kbyte aligned PCI address which points to a 4-kbyte circular buffer in the PCI main memory. * All DMA read/write transactions betw een the host and the PITA are processed via this 4-kbyte address space. ________________________________________ Internal Register: 0Ch B it 31:02 Actual Circular Buffer Pointer Type R Value 31-12 equal to 31-12 of R egister 08, 11-02 actual address B it 1:0 Actual Circular Buffer Pointer Type H Value 00b D escription By reading this register the software has access to the PCI address in the DMA circular buffer address pointer. The bits 31-12 are equal the contents of the Circular Buffer Start Address Register. The bits 11-0 represent the actual dword address in the circular buffer. Preliminary Data Sheet 45 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Register: 1Ch B it 11:0 DMA Write Count Register Type RW D efault Value 000h D escription ________________________________________ Preliminary Data Sheet 46 01.00 PSB 4610 Communication with External Com ponents 5.1.4 IOM-2 Mode 1 ________________________________________ Transmission and Reception of Data in the Circular Buffer Circular Buffer Memory 31 16 15 0 31 16 15 Dont care 0000h 0004h 0008h 0038h 003Ch don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 8 7 B1 0 B2 TX data 1 TX data 2 TX data 3 TX data 4 TX data 5 TX data 6 TX data 7 TX data 8 TX data 9 TX data 10 TX data 11 TX data 12 TX data 13 TX data 14 TX data 15 RX data 1 RX data 2 RX data 3 RX data 4 TX data 20 TX data 21 TX data 22 TX data 23 ________________________________________ Data in Circular Buffer and on Serial DMA Interface D irection Data in Circular Buffer Data on Serial DMA Interface Transmit Bits from circular buffer: [31:16] = don't care [15:8] = B1 [7:0] [7:0] = B2 [7:0] Write to serial DMA interface: Preliminary Data Sheet 47 B1 [7:0] B2 [7:0] 01.00 PSB 4610 Communication with External Com ponents Data in Circular Buffer and on Serial DMA Interface (cont'd) D irection Data in Circular Buffer Data on Serial DMA Interface R eceive Bits to circular buffer: [31:16] = don't care [15:8] = B1 [7:0] [7:0] = B2 [7:0] Read from serial DMA interface: B1 [7:0] B2 [7:0] ________________________________________ Timing Diagram 125 us FSC (i) DCL (i) TXD (o) 8 bit B1 channel DU 8 bit B2 channel DU RXD (i) 8 bit B1 channel DD 8 bit B2 channel DD 16 bit B1, B2 frame, double clock ________________________________________ Internal Registers: 04h B it 5:0 DMA Select Type RW D efault Value 000000b D escription The DMA C ontrol Register includes the 6 bit parameter DMA Select. Used to define the mode for the next DMA transfer: Mode 4 ('001000'): IOM-2 Mode 1 With the DMA_Start bit the DMA transfer can be started or stopped. ________________________________________ Preliminary Data Sheet 48 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Register: 20h B it 1 DCL_Out_En Type RW D efault Value 0b D escription Bit 1='0': The DCL signal is configured as input, i.e. not driven by the PITA. B it 0 Serial_Clock_Select Type RW D efault Value 0b D escription Bit 0='1': The serial controller is driven w ith the external DCL input clock. ________________________________________ Preliminary Data Sheet 49 01.00 PSB 4610 Communication with External Com ponents 5.1.5 IOM-2 Mode 2 ________________________________________ Transmission and Reception of Data in the Circular Buffer Circular Buffer Memory 16 15 31 0 31 16 15 Dont care 0000h 0004h 0008h 0038h 003Ch don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care TX data 1 TX data 2 TX data 3 TX data 4 TX data 5 TX data 6 TX data 7 TX data 8 TX data 9 TX data 10 TX data 11 TX data 12 TX data 13 TX data 14 TX data 15 RX data 1 RX data 2 RX data 3 RX data 4 TX data 20 TX data 21 TX data 22 TX data 23 31 8 7 B1 16 15 Dont care 0 B2 8 7 Monitor 0 0 D, C/I, MR, MX ________________________________________ Data in Circular Buffer and on Serial DMA Interface D irection Buffer Offset Data in Circular Buffer Data on Serial DMA Interface Transmit 0, 2, 4, ... Bits from circular buffer: [31:16] = don't care [15:8] = B1 [7:0] [7:0] = B2 [7:0] Write to serial DMA interface: B1 [7:0] B2 [7:0] Preliminary Data Sheet 50 01.00 PSB 4610 Communication with External Com ponents Data in Circular Buffer and on Serial DMA Interface (cont'd) D irection Buffer Offset Data in Circular Buffer Data on Serial DMA Interface Transmit 1, 3, 5, ... Bits from circular buffer: [31:16] = don't care [15:8] = Monitor 0 [7:0] [7:0] = D,C/I0,MR,MX [7:0] Write to serial DMA interface: Monitor 0 [7:0] D,C/I0,MR,MX [7:0] R eceive 0, 2, 4, ... Bits to circular buffer: [31:16] = don't care [15:8] = B1 [7:0] [7:0] = B2 [7:0] Read from serial DMA interface: B1 [7:0] B2 [7:0] 1, 3, 5, ... Bits to circular buffer: [31:16] = don't care [15:8] = Monitor 0 [7:0] [7:0] = D,C/I0,MR,MX [7:0] Read from serial DMA interface: Monitor 0 [7:0] D,C/I0,MR,MX [7:0] ________________________________________ Timing Diagram 125 us FSC (i) DCL (i) TXD (o) 8 bit B1 channel DU 8 bit B2 channel DU 8 bit Monitor 0 channel DU 2 bit D 4 bit C/I 0 MR MX RXD (i) 8 bit B1 channel DD 8 bit B2 channel DD 8 bit Monitor 0 channel DD 2 bit D 4 bit C/I 0 MR MX 16 bit B1, B2 frame, double clock 16 bit MON0, D, C/I0, MR, MX frame ________________________________________ Preliminary Data Sheet 51 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Registers: 04h B it 5:0 DMA Select Type RW D efault Value 000000b D escription The DMA Control Register includes the 6 bit parameter DMA Select. Used to define the mode for the next DMA transfer: Mode 5 ('010000'): IOM-2 Mode 2 With the DMA_Start bit the DMA transfer can be started or stopped. ________________________________________ Internal Register: 20h B it 1 DCL_Out_En Type RW D efault Value 0b D escription Bit 1='0': The DCL signal is configured as input, i.e. not driven by the PITA. B it 0 Serial_Clock_Select Type RW D efault Value 0b D escription Bit 0='1': The serial controller is driven w ith the external DCL input clock. ________________________________________ Preliminary Data Sheet 52 01.00 PSB 4610 Communication with External Com ponents 5.1.6 IOM-2 Mode 3 ________________________________________ Transmission and Reception of Data in the Circular Buffer Circular Buffer Memory 16 15 31 0 31 16 15 Dont care 0000h 0004h 0008h 0038h 003Ch don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care TX data 1 TX data 2 TX data 3 TX data 4 TX data 5 TX data 6 TX data 7 TX data 8 TX data 9 TX data 10 TX data 11 TX data 12 TX data 13 TX data 14 TX data 15 RX data 1 RX data 2 RX data 3 RX data 4 TX data 20 TX data 21 TX data 22 TX data 23 31 8 7 B1 16 15 Dont care 0 B2 8 7 IC1 0 IC2 ________________________________________ Data in Circular Buffer and on Serial DMA Interface Direction Buffer Offset Data in Circular Buffer Data on Serial DMA Interface Transmit 0, 2, 4, ... Bits from [31:16] [15:8] [7:0] Bits to serial DMA interface: B1 [7:0] B2 [7:0] Preliminary Data Sheet circular buffer: = don't care = B1 [7:0] = B2 [7:0] 53 01.00 PSB 4610 Communication with External Com ponents Data in Circular Buffer and on Serial DMA Interface (cont'd) Direction Buffer Offset Data in Circular Buffer Data on Serial DMA Interface Transmit 1, 3, 5, ... Bits from [31:16] [15:8] [7:0] Write to serial D MA interface: IC1 [7:0] IC2 [7:0] R eceive 0, 2, 4, ... Bits to circular buffer: [31:16] = don't care [15:8] = B1 [7:0] [7:0] = B2 [7:0] Read from serial DMA interface: B1 [7:0] B2 [7:0] 1, 3, 5, ... Write to circular buffer: [31:16] = don't care [15:8] = IC1 [7:0] [7:0] = IC2 [7:0] Read from serial DMA interface: IC1 [7:0] IC2 [7:0] circular buffer: = don't care = IC1 [7:0] = IC2 [7:0] ________________________________________ Timing Diagram 125 us FSC (i) DCL (i) TXD (o) 8 bit B1 channel DU 8 bit B2 channel DU 8 bit IC1 channel DU 8 bit IC2 channel DU RXD (i) 8 bit B1 channel DD 8 bit B2 channel DD 8 bit IC1 channel DD 8 bit IC2 channel DD 16 bit B1, B2 frame, double clock 16 bit IC1, IC2 frame ________________________________________ Preliminary Data Sheet 54 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Registers: 04h B it 5:0 DMA Select Type RW D efault Value 000000b D escription The DMA Control Register includes the 6 bit parameter DMA Select. Used to define the mode for the next DMA transfer: Mode 6 ('100000'): IOM-2 Mode 3 With the DMA_Start bit the DMA transfer can be started or stopped. ________________________________________ Internal Register: 20h B it 1 DCL_Out_En Type RW D efault Value 0b D escription Bit 1='0': The DCL signal is configured as input, i.e. not driven by the PITA. B it 0 Serial_Clock_Select Type RW D efault Value 0b D escription Bit 0='1': The serial controller is driven w ith the external DCL input clock. ________________________________________ Preliminary Data Sheet 55 01.00 PSB 4610 Communication with External Com ponents 5.1.7 IOM-2 Modes - Supplementary Description ________________________________________ Selection of IOM-2 Time Slots The MISC register contains four bits. They are used for masking the time slot on IOM-2. If Bx_MSK (x := [1,4]) is set: * * * * The corresponding value from the TX FIFO is not written to the D U line. FFh is w ritten to this time slot. In IOM-2 mode 1 the bits B3_MSK and B4_MSK have no effect. Data is alw ays transferred from the IOM-2 time slot to the RX-FIFO. ________________________________________ Timing Diagram for all IOM-2 Modes tFSW FSC (i) tFSS tFSH tFSS tFSH DCL (i) t WH RXD (i) tIIS tWL tIIH tCYC tIOD tIOD TXD (o) ________________________________________ Preliminary Data Sheet 56 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Abbreviations for the Timing Diagram Parameter Symbol Unit Limit Values min. max. FSC pulse width t FSW 40 ns FSC setup time tFSS 40 ns FSC hold time t FSH 40 ns D CL cycle time tCYC 244 ns D CL HIGH time tWH 100 ns D CL LOW time tWL 100 ns IOM output data delay t IOD IOM input data setup t IIS 20 ns IOM input data hold tIIH 20 ns 100 ns ________________________________________ Figure of the MISC Register B1 - B4 Mask Bits MISC Register: B1_MSK B2_MSK B3_MSK B4_MSK IOM-2 Mode 1 B1 B2 IOM-2 Mode 2 B1 B2 Monitor 0 D,C/I0,MR,MX IOM-2 Mode 3 B1 B2 IC1 IC2 ________________________________________ Preliminary Data Sheet 57 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Masking of IOM-2 Time slots (Example for IOM-2 Mode 2) IOM-2 DU line TXD (0) B1 B2 B1_MSK 'FFh' D,C/I0,MR,MX Monitor 0 B3_MSK B4_MSK 'FFh' 'FFh' B2_MSK 'FFh' RX FIFO MON0 D,C/I0, MR,MX MON0 D,C/I0, MR,MX B1 B2 B1 B2 TX FIFO IOM-2 DD line RXD (i) B1 B2 Monitor 0 D,C/I0,MR,MX Circular Buffer Memory Data 3 Next IOM-2 frame Data 3 Data 2 Data 2 Don't care Monitor 0 D,C/I0,MR,MX Don't care B1 B2 Data 1 Data 1 Previous IOM-2 frame ________________________________________ Preliminary Data Sheet 58 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Register: 1Ch B it 31:0 MISC (Miscellaneous Register) B it 31 IOM_B1_masking Type RW D efault Value 0b D escription Bit 31='0': Byte B1 is generated out of the circular buffer. Bit 31='1': FFh is transmitted on the B1 time slot. B it 30 IOM_B3_masking Type RW D efault Value 0b D escription Bit 30='0': Byte B2 is generated out of the circular buffer. Bit 30='1': FFh is transmitted on the B2 time slot. B it 29 IOM_Monitor_0 / IC1_masking Type RW D efault Value 0b D escription Bit 29='0': Byte Monitor 0 or IC1 is generated out of the circular buffer. Bit 29='1': FFh is transmitted on the Monitor/IC1 time slot. Monitor is used in IOM-2 mode 2. IC1 is used in IOM-2 mode 3. Preliminary Data Sheet 59 01.00 PSB 4610 Communication with External Com ponents Internal Register: 1Ch (cont'd) B it 28 IOM_Supl_masking / IC2_masking Type RW D efault Value 0b D escription Address:='0': Byte D, C/I0, MR, MX or IC 2 is generated out of the circular buffer. Address:='1': FFh is transmitted on the D, C/I0, MR, MX or IC2 time slot. D, C/I0, MR , MX: U sed in IOM-2 mode 2. IC2: U sed in IOM-2 mode 3 ________________________________________ Preliminary Data Sheet 60 01.00 PSB 4610 Communication with External Com ponents 5.1.8 Single Modem Mode V2.1 ________________________________________ Data in Circular Buffer and on Serial DMA Interface Direction Data in Circular Buffer Data on Serial DMA Interface Transmit Bits from circular buffer: [31:16] = don't care [15:0] = data frame [15:0] Write to serial DMA interface: data frame [15:0] R eceive Bits to circular buffer: [31:16] = don't care [15:0] = data frame [15:0] Read from serial DMA interface: data frame [15:0] ________________________________________ Timing diagrams 125 us FSC (i) DCL (o) TXD (o) 16 bit data RXD (i) 16 bit data 16 bit data frame tFSW FSC (i) tDCI tDCD DCL (o) tWH RXD (i) tWL tISU tIHO tCYC tOD high-Z TXD (o) ________________________________________ Preliminary Data Sheet 61 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Abbreviations for the Timing Diagram Parameter Sym bol FSC pulse width t FSW D CL delay tDCD D CL idle time tDCI D CL cycle time tCYC D CL HIGH time D CL LOW time PCI Clock Cycles 16 Unit Limit Values min. typ. max. 40 ns 480 ns 105 s 40 1200 ns t WH 20 600 ns tWL 20 600 ns D CL duty cycle 45 50 55 % Input data setup t ISU 10 ns Input data hold tIHO 10 ns Output data delay tOD 10 ns ________________________________________ Configuration of the Single Modem Mode V2.1 after a System/Soft Reset * The configuration of the PSB4596 V2.1 in single modem mode is realized by software using the 4-bit General Purpose I/O Interface of the PITA (See "General Purpose I/O Interface" on page 97.). * After a system/soft reset the FSC is an input pin both for - the PITA - the ALIS V2.1 * After a system reset the DC L_Out_En bit must be set to '1' by the host. ________________________________________ Preliminary Data Sheet 62 01.00 PSB 4610 Communication with External Com ponents ________________________________________ PITA Configuration for ALIS V2.1 after a System Reset Serial DMA Interface Mode Ser_Clock_Sel (clock input to Serial DMA interface) ALIS V2.1 0 PC I clock/ 40 DCL_Out_En (DCL Direction) 1 DCL output ________________________________________ Note A Pull Down resistor is required on the board to avoid a floating FSC signal in this situation. ________________________________________ Internal Registers: 04h B it 5:0 DMA Select Type RW D efault Value 000000b D escription The DMA Control Register includes the 6 bit parameter DMA Select. Used to define the mode for the next DMA transfer: Mode 1 ('000001'): Single Modem Mode V2.1 With the DMA_Start bit the DMA transfer can be started or stopped. ________________________________________ Preliminary Data Sheet 63 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Register: 20h B it 1 DCL_Out_En Type RW D efault Value 0b D escription Bit 1='1': The DCL signal is output (open drain) and driven by the PITA. B it 0 Serial_Clock_Select Type RW D efault Value 0b D escription Bit 0='0': The serial controller is driven with the clock signal generated by the internal clock divider. ________________________________________ Preliminary Data Sheet 64 01.00 PSB 4610 Communication with External Com ponents 5.1.9 Single Modem Mode ALIS V3.X ________________________________________ Overview Overview Page Information about the Single Modem Mode ALIS V3.X 65 Internal Registers of the Single Modem Mode V3.X 67 ________________________________________ 5.1.9.1 Information about the Single Modem Mode ALIS V3.X ________________________________________ Data in Circular Buffers, on Serial DMA Interface D irection Data in Circular Buffer Transmit Read from circular buffer: [31:16]= don't care [15:0] = data frame [15:0] Write to serial DMA interface: Write to circular buffer: [31:16]= don't care [15:0] = data frame [15:0] Read from serial DMA interface: R eceive Data on Serial DMA Interface data frame [15:0] data frame [15:0] ________________________________________ Timing Diagram 125 us FSC (i) DCL (i) TXD (o) 16 bit data RXD (i) 16 bit data 8 bit CMD 8 bit write data 8 bit read data 32 bit data / command frame ________________________________________ Preliminary Data Sheet 65 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Note The timing characteristics of the serial D MA interface in Single modem mode V3.X mode are identical to the IOM-2 modes with the only difference that the DC L signal is not a double bit clock, but a single bit clock, similar to Single Modem mode V2.1. ________________________________________ Configuration of the Single Modem Mode V3.X after a System/Soft Reset * Realized by starting the DMA transfer. - Separate from this transfer the command byte and command data byte are written to the ALIS Command Registers in the PITA on addresses 10h. * After a system/soft reset the single modem mode V3.X is in the multiplexed mode because the non multiplexed mode is not supported. * The ALIS V3.X needs some time after an external reset until it has stabilized FSC and DCL. Furthermore as the PITA-2 does not automatically asserts SR ST as a response to a PC I reset the following procedure is recommended to start the communication with the ALIS V3.X: - Assert SRST by resetting bit 25 of internal register 025h - Deassert SRST by setting bit 25 of internal register 025h - Wait 500ms * After this procedure the ALIS V3.X is ready for receiving the first command ________________________________________ PITA Configuration for ALIS V3.X after a System Reset Serial DMA Interface Mode ALIS V3.X Ser_Clock_Sel (clock input to Serial DMA interface 1 2xALIS V3.X 1 ALIS V3.X + second codec 1 DCL_Out_En (DCL Direction) 0 DCL input clock 0 DCL_Out _En 0 ________________________________________ Preliminary Data Sheet 66 01.00 PSB 4610 Communication with External Com ponents 5.1.9.2 Internal Registers of the Single Modem Mode V3.X ________________________________________ Internal Registers: 04h B it 5:0 DMA Select Type RW D efault Value 000000b D escription The DMA Control Register includes the 6 bit parameter DMA Select. Used to define the mode for the next DMA transfer: Mode 2 ('000010'): Single Modem Mode V3.X With the DMA_Start bit the DMA transfer can be started or stopped. ________________________________________ Internal Register: 10h B it 31:0 ALIS Command Register 1 D escription This command register is used for the first command structure in the FSC time slot by the serial controller. B it 31:25 Reserved Type H Value 0b D escription Reserved Preliminary Data Sheet 67 01.00 PSB 4610 Communication with External Com ponents Internal Register: 10h (cont'd) B it 24 New_ALIS_Command_1 Type RW D efault Value 0b D escription Bit 24='1': The host has written a new command to the ALIS Command Resister 1. Bit 24='0': Last command written to the ALIS Command Register 1 by the host is processed and the received data is available in the ALIS Received Data 1 register. This bit is set by software if there is a new command in the ALIS Command 1 Register. After the serial DMA interface has transmitted the new command and the received data is written to the ALIS_Received_Data_1 bits, this bit is reset by the serial DMA interface. B it 23:16 ALIS_Received_Data_1 Type RW D efault Value 00h D escription During a DMA transfer in mode 2 or 3 every time a new command is transferred through the serial DMA interface, the received data is fetched and saved in this register. New command means: The command was written through the PCI interface to the ALIS command register. Transferring a NOP command (FFh or 00h) leads to skipping of the received data. Preliminary Data Sheet 68 01.00 PSB 4610 Communication with External Com ponents Internal Register: 10h (cont'd) B it 15:8 ALIS_Command_1 Type RW D efault Value 00h D escription During a DMA transfer in mode 2 or 3 the contents of this register are transferred as command through the serial DMA interface. After transferring the new command through the serial DMA interface, the register is set to NOP (FFh). B it 7:0 ALIS_Transmit_Data_2 Type RW D efault Value 00h D escription During a DMA transfer in ALIS V3.x mode 2 or 3 the contents of this register are transferred as data through the serial DMA interface. ________________________________________ Preliminary Data Sheet 69 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Register: 14h B it 31:0 ALIS Command Register 2 D efault Value 00000000h B it 31:25 Reserved Type H D efault Value 000h D escription Reserved B it 24 New_ALIS_Command_2 Type RW D efault Value 0b D escription Bit 24='1': The host has written a new command to the ALIS Command 2 Register. Bit 24='0': Last command written to the ALIS Command 2 Register by the host is processed and the received data is available in the ALIS Received Data 2 Register. This bit is set by software if there is a new command in the ALIS Command 2 Register. After the serial controller has transmitted the new command and the received data is written in the ALIS Received Data 2 Register, this bit is reset by the serial controller. Preliminary Data Sheet 70 01.00 PSB 4610 Communication with External Com ponents Internal Register: 14h (cont'd) B it 23:16 ALIS_Received_Data_2 Type RW D efault Value 00h D escription During a DMA transfer in mode 3 every time a new command is transferred through the serial DMA interface, the received data is fetched and saved in this register. New command means: The command was written through the PCI interface to the ALIS V3.X command register. If only a N OP command (FFh or 00h) is transferred the received data is skipped. B it 15:8 ALIS_Command_2 Type RW D efault Value 00h D escription During a DMA transfer in mode 3 the contents of this register are transferred as command through the serial DMA interface. After transferring the new command through the serial DMA interface, the register is set to NOP (FFh). B it 7:0 ALIS_Transmit_Data_2 Type RW D efault Value 00h D escription During a DMA transfer in mode 3 the contents of this register are transferred as data through the serial interface. ________________________________________ Preliminary Data Sheet 71 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Register: 20h B it 1 DCL_Out_En Type RW D efault Value 0b D escription Bit 1='0': The DCL signal is input and driven by the PITA. B it 0 Serial_Clock_Select Type RW D efault Value 0b D escription Bit 0='1': The serial controller is driven w ith the external DCL input clock. ________________________________________ Preliminary Data Sheet 72 01.00 PSB 4610 Communication with External Com ponents 5.1.10 Dual Modem/Modem+Voice Mode ________________________________________ Description * The PITA transmits and receives two 32 bit frames per FSC time slot. * Each 32 bit frames consists of 16 bit data and 16 bit command/data information. * For each of the 32 bit frames the 16 bit transmitted data is read out of the TX FIFO. * The 16 bit transmitted data is written to the RX FIFO. * The command read/write data for the first 32 bit frame is read out/written to the ALIS Command Register 1 (10h) * The command read/write data for the second 32 bit frame is read out/written to the ALIS Command Register 2 (14h). * The internal DMA write counter is incremented every second write transfer to the circular buffer. * A new frame transmission starts if the FSC is sampled '1' at a negative edge of the DCL signal. * The PITA starts driving the TXD line with the first bit of the transmitted data at the next positive D CL edge. * During the transmission the rising DCL edge indicates the start of a bit on the TXD while the falling edge of the DCL is used to latch the RXD signal. * The PITA stops driving the TXD signal with the positive DCL edge when bit 32 of the first or second transmitted frame is on the TXD line. ________________________________________ Preliminary Data Sheet 73 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Data Organization in the Circular Buffer Circular Buffer Memory 31 16 15 0 31 16 15 8 7 TX Data 1 Modem 1 0 16 15 8 7 TX Data 1 Modem 2 0 Dont care 0000h 0004h 0008h 0038h 003Ch don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care TX data 1 TX data 2 TX data 3 TX data 4 TX data 5 TX data 6 TX data 7 TX data 8 TX data 9 TX data 10 TX data 11 TX data 12 TX data 13 TX data 14 TX data 15 RX data 1 RX data 2 RX data 3 RX data 4 TX data 20 TX data 21 TX data 22 TX data 23 31 Dont care ________________________________________ Timing Diagram for the Dual Modem Mode 125 us FSC (i) DCL (i) TXD (o) 16 bit data RXD (i) 16 bit data 8 bit CMD 8 bit write data 16 bit data 8 bit read data 16 bit data 32 bit data / command frame 8 bit CMD 8 bit write data 8 bit read data 32 bit data / command frame ________________________________________ Preliminary Data Sheet 74 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Timing Diagram for the Dual Modem+Voice Mode 125 us FSC (i) DCL (i) TXD (o) 16 bit data RXD (i) 16 bit data 8 bit CMD 8 bit write data 16 bit data 8 bit read data 16 bit data 32 bit data / command frame 32 bit data frame stuffing pattern 'FFh' 16 bit stuffing 'FFh' ________________________________________ Description of the Timing Diagram * * * * The second 32 bit frame only consists of the 16 bit voice data. The voice data is read out the TX FIFO. The voice data is transmitted through the serial DMA interface (MSB first). During this transmission the received 16 bit voice data (MSB first) is written to the RX FIFO. ________________________________________ Internal Registers: 04h B it 5:0 DMA Select Type RW D efault Value 000000b D escription The DMA Control Register includes the 6 bit parameter DMA Select. Used to define the mode for the next DMA transfer: Mode 3 ('000100'): Single D ual Modem/Modem + Voice Mode V3.X With the DMA_Start bit the DMA transfer can be started or stopped. ________________________________________ Preliminary Data Sheet 75 01.00 PSB 4610 Communication with External Com ponents 5.1.11 Loop Back Mode ________________________________________ Description If Loop_Back_Mode is set to '1' transmit data is transferred from the TX FIFO back to the RX FIFO. ________________________________________ Mode Diagram Circular Buffer Memory Data 3 Serial Controller Data 3 Data 2 TX FIFO DMA Controller Data 2 Loop closed RX FIFO Data 1 PITA Data 1 ________________________________________ Preliminary Data Sheet 76 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Internal Register: 28h B it 0 Loop_Back_Mode Type RW D efault Value 0b D escription * Bit 0='0': The serial controller transmits and receives data/ commands through the serial DMA interface (normal operation mode). * Bit 0='1': The serial controller is in loop back mode. - The serial DMA interface reads the data in the transmitting FIFO and writes them in the receiving FIFO. - No data/command transmission will take place on the serial D MA interface. - The serial DMA interface is clocked with the defined Ser_C lock_Sel bit. ________________________________________ Preliminary Data Sheet 77 01.00 PSB 4610 Communication with External Com ponents 5.2 Parallel Interface ________________________________________ Description The PITA has an 8 bit parallel interface to support three external components. This parallel interface is implemented in multiplexed and non multiplexed mode. It works in Infineon/Intel bus mode. The parallel interface is by default in the non multiplexed mode. ________________________________________ Internal Register: 1Ch B it 26 Parallel_interface_mode Type RW D efault Value 0b D escription 0: non multiplexed mode 1: multiplexed mode Bit 24 Softreset_parallel_mode Type RW D efault Value 0b Description 0: Deactivates the reset signal PRST to the application. 1: Activates the high active reset signal PRST to the application. ________________________________________ Preliminary Data Sheet 78 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Mapping between PCI Data and Parallel Interface Data D ata on the PCI bus AD31-0 PCI Byte Enables C/BE3-0 Data on the Parallel Interface Data bus PAD7-0 AD[31-8] = Don't Care AD[7-0] = Parallel Interface Data "XXX0" PAD [7-0] = AD [7-0] AD[31-8] = Don't Care AD[7-0] = Parallel Interface Data "XXX1" No transaction, PCI interface disconnects with Target Abort. ________________________________________ Address Mapping of the 4-kbyte PCI Address Space to the Parallel Interface Address on the PCI address bus AD11-0 Chip Select on the parallel interface Address on the parallel interface address bus PAD7-0 = AD9-2 (mux mode) PA7-0 = AD9-2 (non-mux mode) 3FFh - 000h CS0 FFh - 00h 7FFh - 400h CS1 FFh - 00h BFFh - 800h CS2 FFh - 00h FFFh - C 00h none (not used) ________________________________________ Preliminary Data Sheet 79 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Modes and Timing of the Parallel Interface Modes and Timing Page ALE after System Reset 81 ALE after internal Software Reset 82 ALE after setting the Parallel Interface Mode Bit 83 N on Multiplexed Mode (Write Transaction) 84 N on Multiplexed Mode (Read Transaction) 86 Multiplexed Mode (Write Transaction) 87 Multiplexed Mode (Read Transaction) 88 Transaction Disconnect with Target Abort 89 Transaction Termination with R etry 92 Timing of the Parallel Interface 94 ________________________________________ Preliminary Data Sheet 80 01.00 PSB 4610 Communication with External Com ponents 5.2.1 ALE after System Reset ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 RST PRST ALE WR RD ________________________________________ Description Both ALE and PRST are high during RST and remain high for a maximum of 4 cycles after RST goes deasserted. ________________________________________ Preliminary Data Sheet 81 01.00 PSB 4610 Communication with External Com ponents 5.2.2 ALE after internal Software Reset ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 PRST ALE WR RD ________________________________________ Description * After the internal Soft Reset is deasserted the same behavior as in ALE after System R eset" generated. * The soft reset bit in the internal registers can only be set or reset if the parallel interface is in idle state. * If ALE is high before PAR_RST is asserted, it goes to low one cycle after PRST and takes the new value depending on the PAR_MOD bit in the 6th cycle after PR ST is deasserted. ________________________________________ Preliminary Data Sheet 82 01.00 PSB 4610 Communication with External Com ponents 5.2.3 ALE after setting the Parallel Interface Mode Bit ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 ______ FRAME ____ IRDY _____ TRDY _______ DEVSEL AD31-0 _______ C/BE3-0 _____ STOP ADR1 DATA ADR DATA CMD1 0000 CMD 0000 ALE ________________________________________ Description * The parallel interface is in non multiplexed mode by default. * To set the parallel interface into multiplexed mode: The Parallel_Interface_Mode bit has to be set to '1' after reset. * Two PCI clocks after finishing this data phase the ALE signal is asserted. ________________________________________ Preliminary Data Sheet 83 01.00 PSB 4610 Communication with External Com ponents 5.2.4 Non Multiplexed Mode (Write Transaction) ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 FRAME IRDY TRDY DEVSEL AD31-0 ADR DATA C/BE3-0 CMD XXX0 STOP CS2-0 ALE WR RD PA7-0 PAD7-0 XXXX PCI-ADR[9-2] XXXX PCI-DATA[7-0] ________________________________________ Description * After the address phase on the PCI bus (clock3) and the C/BE0=0 verification the address decoding phase of the target (clocks 3 to 4) is active. * The byte address for the transaction on the parallel interface is generated out of the PCI address AD9-2 by mapping it to the parallel interface address bus PA7-0. * One PCI clock after the PCI data phase is finished the data from the PCI bus is placed on the data bus PAD7-0 (clock 5) and the w rite transaction starts. * The data is placed from the PCI bus on PAD7-0 asserting the WR signal and a CS2-0 signal. * A new access to the parallel interface could be accepted with an address phase at clock 9. Any access before would be cancelled w ith Retry because the PCI Interface is processing the last access. ________________________________________ Preliminary Data Sheet 84 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Example As an example the value 0A4h shall be written at address 005h of the device connected to CS1. In this example the Base Address Register 1 (BAR1) shall contain the address 20004000h. * CS1 is activated for the address space 400h to 7FFh. Therefore the device's address space starts at PCI address BAR1+400h= 20004400h. * Only the lower byte of each 32bit word transferred to and from the PITA-2 over the PCI bus is used for the parallel interface. Therefore the relative PCI address is four times the relative device address: rel. PCI address = four times 005h = 014h. * The absolute PCI address for the data transfer is BAR1+400h+014h=20004414h. * Only the low byte of a 32 bit data word matters, the upper three bytes are ignored by the PITA-2. In order to write the value 0A4h the data word 000000A4 can be written to PCI address 20004414h. ________________________________________ Preliminary Data Sheet 85 01.00 PSB 4610 Communication with External Com ponents 5.2.5 Non Multiplexed Mode (Read Transaction) ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 FRAME IRDY TRDY DEVSEL AD31-0 ADR C/BE3-0 CMD DATA XXX0 STOP CS2-0 ALE WR RD PA7-0 XXXX PCI-ADR[9-2] PAD7-0 XXXX DATA[7-0] ________________________________________ Description * After the address phase on the PCI bus (clock3) and the C/BE0=0 verification the address decoding phase of the target (clocks 3 to 4) is active. * The byte address for the transaction on the parallel interface is generated out of the PCI address AD9-2 by mapping it to the parallel interface address bus PA7-0 (clock 5). * The following PCI clock asserts the signals RD and CS2-0. * After 5 clocks the RD signal is deasserted. * The data from PAD7-0 is fetched. * With the next clock the data is placed on the PCI bus and the data phase is finished by deasserting the TRDY signal. * The 8 bit data from the parallel interface is placed an the last significant byte of the PCI data bus AD7-0. ________________________________________ Preliminary Data Sheet 86 01.00 PSB 4610 Communication with External Com ponents 5.2.6 Multiplexed Mode (Write Transaction) ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 FRAME IRDY TRDY DEVSEL AD31-0 ADR DATA1 C/BE3-0 CMD XXX0 STOP CS2-0 ALE WR RD PAD7-0 PCI-ADR[9-2] PCI-DATA1[7-0] ________________________________________ Description * After the address phase on the PCI bus (clock 3) and the C/BE0=0 verification the address decoding phase of the target (clocks 3 to 4) is active. * The byte address for the transaction on the parallel interface address is generated out of the PCI address AD 9-2 by mapping it to the parallel interface address bus PA7-0. * One PCI clock after the PCI data phase is finished the data from the PCI bus is placed on the data bus PAD7-0 (clock 5) and the w rite transaction starts. * The data is placed from the PCI bus on PAD7-0 asserting the CS2-0 signal. * The ALE signal is deasserted. * With the following PCI clock the data from the PCI bus is placed on PAD7-0 (clock5). * The WR signal is asserted. * A new access to the parallel interface could be accepted with an address phase at clock 11. Any access before would be cancelled with Retry because the PCI Interface is processing the last access. ________________________________________ Preliminary Data Sheet 87 01.00 PSB 4610 Communication with External Com ponents 5.2.7 Multiplexed Mode (Read Transaction) ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FRAME IRDY TRDY DEVSEL AD31-0 ADR(00) C/BE3-0 CMD DATA1 XXX0 STOP CS2-0 ALE WR RD PAD7-0 PCI-ADR[9-2] DATA1[23-16] ________________________________________ Description * After the address phase on the PCI bus (clock 3) and the C/BE0=0 verification the address decoding phase of the target (clocks 3 to 4) is active. * The byte address for the transaction on the parallel interface is generated out of the PCI address AD9-2 by mapping it to the parallel interface address bus PA7-0 (clock 5). * The following PCI clock asserts the ALE signal. * After 2 clocks the ALE signal is deasserted. * The address is held for one more clock. * After 5 clocks the RD signal is deasserted. * At the same time the data is latched in die PCI output registers. * TRDY is asserted on the PCI bus to finish the data phase. * At the next clock the CS2-0 and ALE signals are deasserted. ________________________________________ Preliminary Data Sheet 88 01.00 PSB 4610 Communication with External Com ponents 5.2.8 Transaction Disconnect with Target Abort ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 FRAME IRDY TRDY DEVSEL AD31-0 ADR DATA ADR DATA C/BE3-0 CMD XXX1 CMD XXX1 STOP CS2-0 ALE WR RD PAD7-0 ________________________________________ Preliminary Data Sheet 89 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Description C/BE0 = 1: No transaction is started on selected parallel interface, due to the wrong byte enable. The PC I Master Target Controller disconnects the transaction with target abort. ________________________________________ Configuration Space Register: 04h B it 30 System_Error_Signaled Type RC D efault Value 0b D escription This bit is set by the PITA's PCI Master, if the master asserts the system error signal on the PC I bus. This occurs if a transaction initiated by the PITA is disconnected with target abort. B it 29 Master_Abort_Detected Type RC D efault Value 0b D escription If no fast/medium/slow or subtractive slave reacts to a PCI transaction initiated by the PCI Master, the master will discard the transaction and set this bit. B it 28 Master_Abort_Detected Type RC D efault Value 0b D escription If a PCI transaction initiated by the PCI Master is disconnected with Target Abort, the PCI master will set this bit. The PCI Master is not allowed to start a new PCI transaction, until this bit is deasserted. Preliminary Data Sheet 90 01.00 PSB 4610 Communication with External Com ponents Configuration Space Register: 04h (cont'd) B it 27 Target_Abort_Signaled Type RC D efault Value 0b D escription This bit is set by the PCI interface if a transaction was disconnected w ith Target Abort. The PITA will disconnect transactions with Target Abort if illegal byte enables are detected. B it 8 System_Error_Enable Type RW D efault Value 0b D escription If this bit is asserted, the PC I Master w ill assert the System Error Signal (SERR) if it receives a target abort during a transaction initiated by itself. B it 2 Master_Enable Type RW D efault Value 0b D escription If this bit is set to '0' the PCI Master is not allowed to start any transaction on the PCI Bus. ________________________________________ Preliminary Data Sheet 91 01.00 PSB 4610 Communication with External Com ponents 5.2.9 Transaction Termination with Retry ________________________________________ Description' Retry means that the PITA finishes a transaction without a data transfer by asserting the signal STOP , because the parallel interface processes another transaction. The PCI Master Target Controller has to repeat the transaction until a slave accepts the transaction with data transfer or target abort. This sequence is invisible for the software. ________________________________________ Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 FRAME IRDY TRDY DEVSEL AD31-0 ADR1 DATA1 ADR2 DATA2 C/BE3-0 CMD1 XXX0 CMD2 XXX0 STOP CS2-0 ALE WR RD PAD7-0 PCI-ADR[9-2] PCI-DATA1[7-0] ________________________________________ Preliminary Data Sheet 92 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Explanation of ADR/CMD and ADR2/CMD2 AD R/CMD: The PCI Master Target Controller accepts the write transaction AD R2/CMD2: The second transaction is retried. ________________________________________ Preliminary Data Sheet 93 01.00 PSB 4610 Communication with External Com ponents 5.2.10 Timing of the Parallel Interface ________________________________________ Read Timing tRR tRI RD x CS tRD tDF AD0-AD7 Data ________________________________________ Write Timing tWW tWI WR x CS tWD tDW AD0-AD7 Data ________________________________________ Multiplexed Address Timing tAA tAD ALE WR x CS or RD x CS tALS tAL AD0-AD7 tLA Address ________________________________________ Preliminary Data Sheet 94 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Non Multiplexed Address Timing WR x CS or RD x CS t AS A0-A7 t AH Address ________________________________________ Application Reset and Interrupt Timing tRO D Host write access to the register PRST, SRST previous state valid state tIO D INTO (i) INTA (o) ________________________________________ Preliminary Data Sheet 95 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Abbreviations of the Timing Diagrams Parameter Symbol PCI Clock Cycles Unit Lim it Values min. m ax . ALE pulse width t AA 5 150 ns Address setup time to ALE tAL 1 30 ns Address hold time from ALE tLA 1 30 ns Address latch setup time to WR, RD tALS 1 30 ns Address setup time t AS 1 30 ns Address hold time t AH 1 30 ns ALE guard time t AD 1 30 ns R D pulse width tRR 5 150 ns D ata output delay from RD tRD 5 150 ns D ata float from R D t DF 1 30 ns R D control interval t RI 5 150 ns W pulse width tWW 3 90 ns D ata setup time to W x CS tDW 2 60 ns D ata hold time W x CS tWD 1 30 ns W control interval tWI 3 90 ns R eset Output Delay tROD 3 90 ns Interrupt Output Delay t IOD 2 60 ns ________________________________________ Preliminary Data Sheet 96 01.00 PSB 4610 Communication with External Com ponents 5.3 General Purpose I/O Interface ________________________________________ Overview Overview Page Information about the GP I/O Interface 98 Timing of the GP I/O Interface 100 Internal Registers of the GP I/O Interface 101 Input Mode 107 Output Mode 109 Interrupt Mode 111 U sage of the GP I/O Interface as ALIS V2.1 Control Interface 113 ________________________________________ Preliminary Data Sheet 97 01.00 PSB 4610 Communication with External Com ponents 5.3.1 Information about the GP I/O Interface ________________________________________ Description For additional access to external devices with a slow interface behavior a 4 bit General Purpose I/O interface is implemented in the PITA. ________________________________________ Pinning Pin Pin Name General Purpose I/O Function SPI EEPROM Function 2 GP0 I/O/Int. SO 3 GP1 I/O/Int. SI 4 GP2 I/O/Int. SCK 5 GP3 I/O/Int. - ________________________________________ Application Interrupt * The PCI interface supports a separate interrupt input with programmable polarity. * The four pins of the general purpose I/O interface can be used as additional interrupt inputs. * Each of these five interrupts has an Interrupt_Enable bit and an Interrupt_Control_Status bit. * For the separate input the enable an polarity bits are located in the Interrupt Control Register. * For the General Purpose I/O the enable bits are located in the Interface C ontrol Register. ________________________________________ Preliminary Data Sheet 98 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Control Registers for GPx Pins R egister Register Bit Description Interrupt C ontrol Register - ICR GPx_INT GP Interrupt Status GPx_INT_En GP Interrupt Enable GPx_OUT_En GP Output Enable GPx_OUT GP Output Value GPx_IN GP Input Value GP I/O Interface Control Register ________________________________________ Preliminary Data Sheet 99 01.00 PSB 4610 Communication with External Com ponents 5.3.2 Timing of the GP I/O Interface ________________________________________ Timing Diagram tOD Host write access GPx configured as output GP0-3 (o) valid state tISU tIHO Host read access GP0-3 (i) GPx configured as input valid state tIOD GP0-3 (i) GPx configured as interrupt input INTA (o) ________________________________________ Abbreviations of the Timing Diagram Parameter Symbol Limit Values m in. Unit max. 90 ns GPx Output Data Delay t OD GPx Input Data Setup t ISU 30 ns GPx Input Data Hold tIHO 30 ns GPx Interrupt Output D elay tIOD Preliminary Data Sheet 100 90 ns 01.00 PSB 4610 Communication with External Com ponents 5.3.3 Internal Registers of the GP I/O Interface ________________________________________ Internal Register: 00h B it 5 GP3_INT Type RC D efault Value 0b D escription The GP3 pin can be used as 'active low' interrupt input if GP3_Int_En='1' and GP3_Out_En='0'. The bit is set to '1' if both are true and low is detected at this pin. B it 4 GP2_INT Type RC D efault Value 0b D escription The GP2 pin can be used as 'active low' interrupt input if GP2_Int_En='1' and GP2_Out_En='0'. The bit is set to '1' if both are true and low is detected at this pin. B it 3 GP1_INT Type RC D efault Value 0b D escription The GP1 pin can be used as 'active low' interrupt input if GP1_Int_En='1' and GP1_Out_En='0'. Preliminary Data Sheet 101 01.00 PSB 4610 Communication with External Com ponents Internal Register: 00h (cont'd) B it 2 GP0_INT Type RC D efault Value 0b D escription The GP0 pin can be used as 'active low' interrupt input if GP0_Int_En='1' and GP0_Out_En='0'. ________________________________________ Internal Register: 18h B it 27 GP3_Int_En Type RW D efault Value 0b D escription Bit 27='1': GP3 is configured as input, the pin is used as an interrupt input with GP3_Int_en as corresponding bit in the Interrupt Control Register. Bit 27='1': GP3 is not used as an interrupt pin. B it 26 GP2_Int_En Type RW D efault Value 0b D escription Bit 26='1': GP2 is configured as input, the pin is used as an interrupt input with GP2_Int_en as corresponding bit in the Interrupt Control Register. Bit 26='0': GP2 is not used as an interrupt pin. Preliminary Data Sheet 102 01.00 PSB 4610 Communication with External Com ponents Internal Register: 18h (cont'd) B it 25 GP1_Int_En Type RW D efault Value 0b D escription Bit 25='1': GP1 is configured as input, the pin is used as an interrupt input with GP1_Int_en as corresponding bit in the Interrupt Control Register. Bit 25='0': GP1 is not used as an interrupt pin. B it 24 GP0_Int_En Type RW D efault Value 0b D escription Bit 24='1': GP0 is configured as input, the pin is used as an interrupt input with GP0_Int_en as corresponding bit in the Interrupt Control Register. Bit 24='0': GP0 is not used as an interrupt pin. B it 19 GP3_Out_En Type RW D efault Value 0b D escription Bit 19='1': GP_3 is configured as output pin. Bit 19='0': GP_3 is configured as input pin. B it 18 GP2_Out_En Type RW D efault Value 0b D escription Bit 18='1': GP_2 is configured as output pin. Bit 18='0': GP_2 is configured as input pin. Preliminary Data Sheet 103 01.00 PSB 4610 Communication with External Com ponents Internal Register: 18h (cont'd) B it 17 GP1_Out_En Type RW D efault Value 0b D escription Bit 17='1': GP_1 is configured as output pin. Bit 17='0': GP_1 is configured as input pin. B it 16 GP0_Out_En Type RW D efault Value 0b D escription Bit 16='1': GP_0 is configured as output pin. Bit 16='0': GP_0 is configured as input pin. B it 11 GP3_IN Type R D escription Actual Value on the GP3 pin (pin feedback) B it 10 GP2_IN Type R D escription Actual Value on the GP2 pin (pin feedback) B it 9 GP1_IN Type R D escription Actual Value on the GP1 pin (pin feedback) Preliminary Data Sheet 104 01.00 PSB 4610 Communication with External Com ponents Internal Register: 18h (cont'd) B it 8 GP0_IN Type R D escription Actual Value on the GP0 pin (pin feedback) B it 3 GP3_OUT Type RW D efault Value 0b D escription The GP3 pin is driven with the value written to this output register if the GP3_OUT_En is set to '1'. B it 2 GP2_OUT Type RW D efault Value 0b D escription The GP2 pin is driven with the value written to this output register if the GP2_OUT_En is set to '1'. B it 1 GP1_OUT Type RW D efault Value 0b D escription The GP1 pin is driven with the value written to this output register if the GP1_OUT_En is set to '1'. Preliminary Data Sheet 105 01.00 PSB 4610 Communication with External Com ponents Internal Register: 18h (cont'd) B it 0 GP0_OUT Type RW D efault Value 0b D escription The GP0 pin is driven with the value written to this output register if the GP0_OUT_En is set to '1'. ________________________________________ Preliminary Data Sheet 106 01.00 PSB 4610 Communication with External Com ponents 5.3.4 Input Mode ________________________________________ Description For using a general purpose I/O pin as input pin, the control register must be configured as follows: GPx_OUT_En = `0' (Output disabled) GPx_INT_En (Interrupt disabled) = `0' (x := [0, 3]) Description of the internal register 18h on page 102. The GPx_OUT and GPx_INT bits can be treated as don't care in this mode. The current signal value at the pin GPx can be read from register bit GPx_IN. ________________________________________ Internal Structure of a GPx Input Pin D Q GPx Q GPx_IN ________________________________________ Timing Diagram tISU tIHO Host read access GP0-3 (i) GPx configured as input valid state ________________________________________ Preliminary Data Sheet 107 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Abbreviations of the Timing Diagram Parameter Symbol Limit Values m in. Unit max. GPx Input Data Setup t ISU 30 ns GPx Input Data Hold tIHO 30 ns ________________________________________ Preliminary Data Sheet 108 01.00 PSB 4610 Communication with External Com ponents 5.3.5 Output Mode ________________________________________ Description For using a general purpose I/O pin as output pin, the control register must be configured as follows: GPx_OUT_En = `1' (Output enabled) GPx_INT_En `don't care' = (x := [0, 3]) Description of the internal register 18h on page 102. The GPx_IN and GPx_INT register bits can be treated as don't care in this mode. The GPx pin will drive the connected signal line with the value defined in the GPx_OUT register bit, which is programmed by the host. ________________________________________ Internal Structure of a GPx Output Pin D Q Q GPx_Out D GPx En Q Q GPx_Out_En ________________________________________ Preliminary Data Sheet 109 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Timing Diagram tOD Host write access GPx configured as output GP0-3 (o) valid state ________________________________________ Abbreviation of the Timing Diagram Parameter Symbol Limit Values m in. GPx Output Data Delay t OD Unit max. 90 ns ________________________________________ Preliminary Data Sheet 110 01.00 PSB 4610 Communication with External Com ponents 5.3.6 Interrupt Mode ________________________________________ Description For using a general purpose I/O pin as output pin, the control register must be configured as follows: GPx_OUT_En = `1' (Output disabled) GPx_INT_En (Interrupt enabled) = `1' (x := [0, 3]) Description of the internal register 18h on page 102. The GPx_OUT register bit can be treated as don't care in this mode. The GPx pin acts as an active low interrupt input pin. If the device detects '0' at the GPx pin * the GPx_INT register is set to '1' * an interrupt on the PCI bus is generated * the current state of the GPx pin can be read from GPx_IN bit or can be treated as don't care. ________________________________________ Internal Structure of a GPx Interrupt Input pin D Q 1 x GPx 3 Q GPx_IN >=1 0 INTA 4 ________________________________________ Timing Diagram tIOD GP0-3 (i) GPx configured as interrupt input INTA (o) ________________________________________ Preliminary Data Sheet 111 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Abbreviation of the Timing Diagram Parameter Symbol Limit Values m in. GPx Interrupt Output D elay tIOD Unit max. 90 ns ________________________________________ Preliminary Data Sheet 112 01.00 PSB 4610 Communication with External Com ponents 5.3.7 Usage of the GP I/O Interface as ALIS V2.1 Control Interface ________________________________________ The serial control interface of the ALIS V2.1 can be realized by software using the General Purpose I/O pins. The GP3 pin is used as CS pin while the other three GPx pins are shared with the SPI EEPROM Interface. The INT0 pin of the PITA can be programmed to be active on a H level. Therefore this pin can be connected directly to the INT pin of the ALIS. The GP3 pin is driven high during the automatic EEPR OM configuration phase after a system reset to disable the ALIS V2.1 control interface. Pin description on page 162. ________________________________________ Description PITA Signals ALIS Signals Description GP3 Out CS Chip select (active low ), for enabling the PSB4596 Control Interface. GP2 Out DCLK Clock signal for the Control Interface. (PSB4596 accepts 1 kHz to 1024 kH z) GP1 In DOUT Data input for PITA, data output from PSB4596. Data input is latched at the negative DCLK edge. GP0 Out DIN Data output from PITA, data input for PSB4596. Data output changes with the rising DCLK edge. INT0 In INT Interrupt signal (high active) SRST Out RESET Reset signal (low active) ________________________________________ Preliminary Data Sheet 113 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Timing Diagram for a Write Transaction with two Data Bytes transmitted Control Frame GP3 (o) / CS (i) GP2 (o) / DCLK (i) GP1 (i) / DOUT (o) GP0 (o) / DIN (i) High Z 76 54321076 54321076 543210 Control Data Byte 1 Data Byte 2 ________________________________________ Timing Diagram for a Read Access with one Data Byte received via DOUT Control Frame GP3 (o) / CS (i) GP2 (o) / DCLK (i) GP1 (i) / DOUT (o) GP0 (o) / DIN (i) High Z 765432 10765432 10 High Z 7654321 0 Control Identification Data Byte 1 ________________________________________ Preliminary Data Sheet 114 01.00 PSB 4610 Communication with External Com ponents 5.4 SPI EEPROM Interface ________________________________________ Overview Overview Page Information about the SPI EEPROM Interface 116 Timing of the SPI EEPROM Interface 119 Internal Registers for the SPI EEPROM Interface 121 ________________________________________ Preliminary Data Sheet 115 01.00 PSB 4610 Communication with External Com ponents 5.4.1 Information about the SPI EEPROM Interface ________________________________________ Description Three pins are used to provide an SPITM-compatible serial interface to a 256 x 8 bit EEPROM. These pins also do double-duty as part of the General Purpose Interface. Two other pins are also used to select the EEPROM chip and to enable/ disable the automatic reconfiguration of the configuration space by the EEPROM. This would occur after a system reset. The EEPROM can be used for: * Automatic reconfiguration of the PITA. * Customer specific purposes (e.g. storage of serial board numbers). ________________________________________ Automatic reconfiguration of the PITA Parts of the PCI Configuration Space can be configured with data from this external EEPROM after system reset. The follow ing sequence is processed by the PITA: * The PITA checks: - Whether the ELD (EEPR OM_Load) pin is clamped to '1'. - Whether the first byte in the EEPROM (address location 00h) is AAh. * If the first step was successful, the PITA starts: - Reading out four bytes starting with address 01h. - Writing the read values in the configuration space address 00h. - Reading out the next four bytes. - Writing the read values in the configuration space address 04h. - And so on. ________________________________________ Note During the configuration phase, all access to the PCI interface are answered with 'Retry' by the PITA. ________________________________________ Preliminary Data Sheet 116 01.00 PSB 4610 Communication with External Com ponents ________________________________________ Using the EEPROM for customer specific purposes The contents of the EEPROM can be programmed by writing a command to the EEPROM Control Register and initiating a read/write transaction to the EEPROM. ________________________________________ Note If the automatic reconfiguration of the PITA is used (ELD pin clamped to '1'), only those addresses in the EEPROM not mapped to the PCI configuration space should be used. ________________________________________ Starting a read or write transaction The contents of the EEPROM can be programmed by writing a command to the EEPROM Control Register and initiating a read/write transaction to the EEPROM. * The host w rites - The EEPROM Command value before the next EEPROM transfer is started. - The EEPROM Byte Address value for read or write access. - The EEPROM Data value for the 'Write Status Register' and 'Write Data to Memory Array'. * The host sets the EEPROM_Start bit. * If the EEPROM interface detects the asserted EEPROM_Start bit; it - Interprets the EEPROM Command. * Starts the read or write transaction to the connected EEPROM. * If the transactions are started via the EEPROM Control register, then the EEPROM interface does not check for a connected EEPROM. ________________________________________ Preliminary Data Sheet 117 01.00 PSB 4610 Communication with External Com ponents ________________________________________ After finishing the transaction: * The EEPROM control module: - Deasserts the EEPROM_Start bit. - Generates an interrupt in the EEPROM Control Int Register, if the EEPROM_Control_Int_en bit is set to '1'. * If The EEPROM Command Register is set to RDSR or READ, then the value of the EEPROM is available in the EEPROM Data Register. ________________________________________ Connection of an ALIS V2.1 device to the Serial Control Interface For the connection of an ALIS V2.1 device to the Serial Control Interface of the PITA the GP3 pin is additionally used as low active chip select signal CS to the ALIS V2.1. The GP3 pin is always driven 'high' and therefore the ALIS V2.1 interface is inactive during the phase of automatic initialization of the PCI Configuration Space. ________________________________________ Preliminary Data Sheet 118 01.00 PSB 4610 Communication with External Com ponents 5.4.2 Timing of the SPI EEPROM Interface ________________________________________ Timing Diagram tCSI EPCS (o) tCSS tCYC tOR tOF tCSH SCK (o) tCLH tCLL tISU tIHO SO (i) LSB in tOSU tOHO tOD SI (o) high-Z LSB out ________________________________________ Abbreviations of the Timing Diagram Parameter Symbol Limit Values min. Unit max. C hip Select Setup Time t CSS 500 ns C hip Select Hold Time tCSH 500 ns C hip Select Inactive t CSI 500 ns C lock Cycle Time tCYC 1000 ns C lock HIGH Time t CLH 410 ns C lock LOW Time t CLL 410 ns C lock Output Rise Time tOR 2 s C lock Output Fall Time t OF 2 s Input Data Setup Time t ISU 100 ns Input Data Hold Time tIHO 100 ns Output Data Setup Time tOSU Preliminary Data Sheet 119 500 ns 01.00 PSB 4610 Communication with External Com ponents Abbreviations of the Timing Diagram (cont'd) Parameter Symbol Limit Values min. Output Data Hold Time t OHO 0 Unit max. 500 ns Output Disable Time tOD 500 ns Write Cycle Time t WC 10 ms ________________________________________ Note The SCK is a strobed clock signal (i.e. it is only active as long as valid data is transferred on SI/SO line) and output data is written on the falling edge and input data is latched on the rising edge. Although the first SCK edge is positive, the PITA drives the first valid bit on SI (output) with the falling edge of EPCS, so the minimum setup time with respect to the first SCK rising edge is guaranteed. ________________________________________ Preliminary Data Sheet 120 01.00 PSB 4610 Communication with External Com ponents 5.4.3 Internal Registers for the SPI EEPROM Interface ________________________________________ Internal Register: 00h B it 28 EEPROM_Control_Int_En Type RW D efault Value 0b D escription Enable for the EEPROM_Control_Int interrupt bit B it 12 EEPROM_Control_Int Type RC D efault Value 0b D escription The EEPROM_Control_Int_En bit and the EEPROM are set to '1' if the transaction is finished. ________________________________________ Internal Register: 24h B it 31:0 EEPROM Control Register D efault Value 00000000h B it 24 EEPROM_Start Type RW D efault Value 0b D escription Bit 24='1': An EEPROM transaction is started with the EEPROM Command, EEPROM Data and EEPROM Byte Address. BIT 24='0': An EEPROM transaction can be started. Preliminary Data Sheet 121 01.00 PSB 4610 Communication with External Com ponents Internal Register: 24h (cont'd) B it 23:16 EEPROM Command Type RW D efault Value 00h D escription The following SPI commands are supported: '00000110': WR EN Set Write Enable Latch '00000100': WR DI Reset Write Enable Latch '00000101': RDSR Read Status Register '00000001': WR SR Write Status Register '00000011': READ Read Data from Memory Array '00000010': WR ITE Write Data to Memory Array 'OTHERS': No action B it 15:8 EEPROM Byte Address Type RW D efault Value 00h D escription Byte Address for the next EEPROM transaction. B it 7:0 EEPROM Data Type RW D efault Value 00h D escription * Transaction with a read command: After the transaction has been finished this register contains the byte that has been read from the EEPROM. * Transaction with a w rite command: The contents of this register will be written to the EEPROM Byte Address if the connected EEPROM after the EEPROM_Start bit is set. read or write ________________________________________ Preliminary Data Sheet 122 01.00 PSB 4610 Power Managem ent 6 Power Management ________________________________________ Overview Overview Page Information about the Power Supply Concept 124 Information about the Power Management States 126 C onfiguration Space Registers of the Power Management 131 Electrical Characteristics 146 C ompatibility Issues 147 ________________________________________ Preliminary Data Sheet 123 01.00 PSB 4610 Power Managem ent 6.1 Information about the Power Supply Concept ________________________________________ Three different Power Supplies The PITA-2 has three different power supplies. It may be helpful for the system design to understand the scope of each of these supplies. * VIO This supply is internally connected to all signals intended for the PCI bus (pin numbers 8-12, 16-60 and 64). VIO can be either 3.3V or 5V and is derived from the VIO supply of the PCI bus. This supply has an effect on the thresholds of the input structure in order to comply with the PCI bus specification. Therefore the PITA-2 can be operated in either 5V or 3.3V signaling environment as specified in the PCI Local Bus Specification Revision 2.2 * VD D3 This supply powers the same pins as listed for VIO. It is used for the output drivers of the PCI bus signals and must be limited to 3.3V at all times (even when VIO is 5V). This supply does not power the internal logic of the PITA-2. It does, however, power the local bus signals (pin numbers 1-7, 65-74, 76-87 and 90-100). If this supply is present the input signals on the local bus signals can be as high as 5V. * VA UX This supply also pow ers the local bus signals (pin numbers 1-7, 65-74, 76-87 and 90-100) as well as the internal logic. This power supply is 3.3V only. If this supply is not present, the PITA-2 can not generate a PME event, the output voltage on any of the above mentioned signals is undefined and the input voltage at any of these pins must not exceed VAUX by more than 0.3V. If this supply is present, then the PITA is fully operational and the input signals on the local bus signals can be as high as 5V. ________________________________________ Preliminary Data Sheet 124 01.00 PSB 4610 Power Managem ent ________________________________________ Summary Information Supply Voltage Comm ent VIO 3.3V or 5V For PCI bus only, affects input threshold, almost no current. Should be present at all times. VDD3 3.3V For PCI and local bus, decouples internal logic from PCI bus. Should be present at all times except D3cold. If present, the local bus signals can tolerate 5V. VAUX 3.3V Supplies internal logic, must be present for 5V tolerance of local (non PC I signals) input signals. Can be switched off when D3cold is not supported. ________________________________________ Preliminary Data Sheet 125 01.00 PSB 4610 Power Managem ent 6.1.1 Information about the Power Management States ________________________________________ Description The PITA-2 supports the Power Management states D0, D1, D2, D3hot and D3cold. The PITA-2 can assert the PME signal even if the PCI clock (CLK) is not running. Furthermore the PITA-2 has a separate power supply (Vaux) which meets the power constraints (20 mA) for the PCI Vaux supply (disabled slots). Therefore the PITA-2 fully supports the D3cold state. A separate Application Note describes a power supply circuitry for a D3cold enabled PITA-2. Please note that bits 8 (PME_En) and 15 (PME_Status) of configuration space register 44h are not affected by a PCI reset. This behavior allows the PCI device driver to determine the PCI device(s) that signalled the PME event. ________________________________________ D0 * The D0 state represents the default state of the internal logic after a system reset. * After a system reset the PCI interface has to be initialized before being used. * The PITA-2 responds only to configuration accesses while not completely initialized. * After initialization the PITA-2 is fully operational. ________________________________________ D1 * D1 is a light sleep state. * The PITA-2 supports the D1 state by default if this state is not disabled by an EEPROM configuration. * The PITA-2 PCI function can be set to the D 1 state by software. * The PITA-2 PCI function only responds to PCI configuration accesses. * All accesses to the memory spaces defined by the Base Address Registers are disabled. * The only PCI bus operation the PCI interface is allowed to initiate is the assertion of the PME signal. * Transition to D0 by software is possible. ________________________________________ Preliminary Data Sheet 126 01.00 PSB 4610 Power Managem ent ________________________________________ D2 * By default the support of the D2 state is disabled in the PITA-2. * D2 can be enabled by configuration by an EEPROM. * Same state behavior as described for the state D1. ________________________________________ D3 * Same state behavior as described for the state D1. * The only legal state transitions from D3 to D0 are: - by software reset; the software has to perform a fully reinitialization of the PC I function including the PCI Configuration Space. - by system reset ________________________________________ D3hot * Power and clock are still available to the PITA-2. * Power and clock can be returned to D 0 by software. * State behavior as described for the state D 3. ________________________________________ D3cold (Standby) * * * * D3cold is a "power off" state. The PCI clock is turned off. The PCI bus pow er Vcc has been disconnected. As long as the PITA-2 is supplied with power on the Vaux pins it can still assert PME. * The PITA-2 can assert PME even if the PCI clock is not available. ________________________________________ Preliminary Data Sheet 127 01.00 PSB 4610 Power Managem ent 6.1.2 Considerations about Power Consumption and Reporting ________________________________________ Definitions First of all it is important to distinguish between a PCI component and a PCI device. The PCI component is the circuitry that is interfacing the PCI bus. As an example the PITA-2 is a PCI bus component. The PCI device is the circuitry designed to perform a specific function (e.g. a modem) including the PCI component. Therefore for all power consumption calculations or measurements it is important to add up the power requirements of all the circuitry that is active in a given state. Furthermore it is important to distinguish between PCI slots that are disabled and those that are enabled. ________________________________________ Power Consumption A disabled PCI slot may draw up to 20 mA from power supply VAUX. A PCI device which occupies a disabled slot does not have to support D3cold state. As the PITA-2 draws a maximum of 19 mA it can be left connected to VAUX all the time provided that the external circuitry is switched off (by using the PME_En signal). An enabled PCI slot may consume up to 375 mA w hen in D3cold state. This leaves enough headroom (356 mA) for external circuitry to trigger the PITA-2 for a PME event. ________________________________________ Reporting The PCI Bus Power Management Interface Specification specifies two ways that allow the operating system or other softw are to determine the power consumption of a PCI device: * Coarse reporting by register 40h:8-6 (Aux_C urrent) * Extended reporting by using the data select mechanism The PITA-2 supports both ways. It is up to the PCI device designer to choose the reporting mechanism and also which values are reported. Extended reporting overrides coarse reporting. ________________________________________ Preliminary Data Sheet 128 01.00 PSB 4610 Power Managem ent ________________________________________ Coarse Reporting This mechanism is implemented by the Aux Current field (register 40h). It is only possible to report a single range for the max. current drawn by the PCI device and this range only applied for state D3cold. ________________________________________ Assignments 8 7 6 Max. Current (mA) 1 1 1 375 1 1 0 320 1 0 1 270 1 0 0 220 0 1 1 160 0 1 0 100 0 0 1 55 0 0 0 0 (self powered) ________________________________________ Extended Reporting This mechanism allows a detailed power consumption reporting. It is possible to report individual power limits for each pow er state. Furthermore there is no predefined range w hich may fit more or less but all values can be specified by the PC I designers as needed. The actual data is retrieved by first selecting a specific item (e.g. D2 Power Consumed) by writing a select code into the Data Select field in register 44h. Then the PITA-2 mirrors the selected values to the Data and the Data Scale field of register 44h. The software can then read these two values. The table below shows the way the Data Scale field should be interpreted for single function PCI devices. Preliminary Data Sheet 129 01.00 PSB 4610 Power Managem ent ________________________________________ Data Selected -- Data Reported Data Select D ata Reported 0 D 0 Pow er Consumed 1 D 1 Pow er Consumed 2 D 2 Pow er Consumed 3 D 3 Pow er Consumed 4 D 0 Pow er Dissipated 5 D 1 Pow er Dissipated 6 D 2 Pow er Dissipated 7 D 3 Pow er Dissipated ________________________________________ Note The unit for all values is Watts. ________________________________________ The Data Scale field modifies the value of the Data field as follows: Data Scale Modifier 0 Unknown 1 x 0.1 2 x 0.01 3 x 0.001 The actual data can be stored in the external EEPROM. At reset the PITA-2 loads the data into the appropriate registers. Preliminary Data Sheet 130 01.00 PSB 4610 Power Managem ent 6.1.3 Configuration Space Registers of the Power Management ________________________________________ Configuration Register related to Power Management There are basically two types of configuration registers related to power management: * Control Registers * Data Registers The control registers (40h and 44h) define the capabilities and the behavior of the PITA-2. As an example bit 26 in register 40h defines whether the PITA-2 supports D2 or not. The data registers (48h, 4Ch and 50h) reflect the power consumption of the whole PC I device for eight different configurations. A configuration is selected by a value in the data select field of register 44h. The corresponding value is then placed into the data field of register 44h. The actual values have no effect on the operation or power consumption of the PITA-2. These values are calculated or measured by the PCI device designer and can be stored in the external EEPROM. Please note that the PCI device includes all external circuitry and usually consists not only of the PITA-2. Register 34h is merely a pointer to the first register of the power management configuration space and hardwired to 40h. ________________________________________ Preliminary Data Sheet 131 01.00 PSB 4610 Power Managem ent ________________________________________ Configuration Space Register: 34h B it 31:8 Reserved Type H Value 000000h D escription Reserved B it 7:0 Cap_Ptr Type H Value 40h D escription The Capabilities Pointer points to the first Power Management Register in the PCI Configuration Space. ________________________________________ Preliminary Data Sheet 132 01.00 PSB 4610 Power Managem ent ________________________________________ Configuration Space Register: 40h B it 31:0 Power Management Capabilities (PMC) B it 31 PME_Support_D3cold Type E D efault Value 0b D escription 0: PME cannot be asserted in state D3cold 1: PME can be asserted in state D3cold B it 30 PME_Support_D3hot Type E D efault Value 0b D escription 0: PME cannot be asserted in state D3hot 1: PME can be asserted in state D3hot B it 29 PME_Support_D2 Type E D efault Value 0b D escription 0: PME cannot be asserted in state D2 1: PME can be asserted in state D2 Preliminary Data Sheet 133 01.00 PSB 4610 Power Managem ent Configuration Space Register: 40h (cont'd) B it 28 PME_Support_D1 Type E D efault Value 1b D escription 0: PME cannot be asserted in state D1 1: PME can be asserted in state D1 B it 27 PME_Support_D0 Type E D efault Value 0b D escription 0: PME cannot be asserted in state D0 1: PME can be asserted in state D0 B it 26 D2_Support Type E D efault Value 0b D escription * Not supported from the PITA-2 by default. * Support can be enabled by EEPROM. B it 25 D1_Support Type E D efault Value 1b D escription * The PITA-2 supports the D 1 Power state by default. * Can be disabled by EEPROM. Preliminary Data Sheet 134 01.00 PSB 4610 Power Managem ent Configuration Space Register: 40h (cont'd) B it 24:22 Aux Current Type E D efault Value 000b D escription This field can be used to report the VAUX current drawn by the PCI device if the Data Register in register 44h is not used. If the Data Register is used, this field must read 000b. Otherwise the following assignments apply: 001: 010: 011: 100: 101: 110: 111: up to 55mA up to 100mA up to 160 mA up to 220 mA up to 270 mA up to 320 mA up to 375 mA B it 21 DSI (Device Specific Initialization) Type E Value 1b D escription Indicates that the PITA-2 requires a specific initialization sequence following the transition to D0 state (uninitialized). B it 20 Reserved Type H Value 0b D escription Reserved Preliminary Data Sheet 135 01.00 PSB 4610 Power Managem ent Configuration Space Register: 40h (cont'd) B it 19 PME_Clock Type E D efault Value 0b D escription The PITA-2 can assert PME without a running clock. Whether this bit must be set is therefore dependant on the external circuitry that triggers the PITA-2 for a PME event. 0: no clock required 1: clock required B it 18:16 Version Type E D efault Value 010b D escription The value 010b indicates that the device complies with the Revision 1.1 of the PCI Pow er Management Interface Specification. B it 15:8 Next_Item_Ptr Type H Value 00h D escription No next item B it 7:0 Capabiltity_ID Type H Value 01h D escription Indicates that the data structure is currently pointed to the PCI Power Management data structure. Preliminary Data Sheet 136 01.00 PSB 4610 Power Managem ent ________________________________________ Configuration Space Register: 44h B it 31:24 DATA_Register Type H Value 00h D escription Depending on the Data_Select field (Bit 12:9) parts of the Power Data register (48h) are mapped to this register. B it 23:16 PMCSR_BSE (Bridge support extension) Type H Value 00h D escription not used B it 15 PME_Status Type RC D efault Value none (sticky bit) D escription This bit is set when the PCI interface asserts the PME signal independent of the state of the PME_EN bit. B it 14:13 Data_Scale Type H Value 00b D escription Depending on the Data_Select field (Bit 12:9) parts of the Power_Data register are mapped to this register. Preliminary Data Sheet 137 01.00 PSB 4610 Power Managem ent Configuration Space Register: 44h (cont'd) B it 12:9 Data_Select Type RW D efault Value 0h D escription * Values from 0 - 7 are supported: Parts of the Pow er_Data register are mapped to the DATA register and the Data_Scale field. * Values from 8 - 15: Zero values are mapped to the DATA register and the Data_Select field. B it 8 PME_En Type RW D efault Value none (sticky bit) D escription Enables or disables the PITA-2 to assert the PME signal. PME_En='0': Assertion of the PME signal is disabled. PME_En='1': The device is enabled to assert the PME signal. B it 7:2 Reserved Type H Value 00h D escription Reserved Preliminary Data Sheet 138 01.00 PSB 4610 Power Managem ent Configuration Space Register: 44h (cont'd) B it 1:0 Power_State Type RW D efault Value 00b D escription Power_State='00': Power_State='01': Power_State='10': Power_State='11': D0 state (supported by the PITA-2) D1 state (supported by the PITA-2) D2 state (not supported by default) D3hot state (supported by the PITA-2). ________________________________________ Preliminary Data Sheet 139 01.00 PSB 4610 Power Managem ent ________________________________________ Configuration Space Register: 48h B it 31:30 Reserved Type H Value 00b B it 29:28 Data Scale for Data Select = 2 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 2. B it 27:20 Data for Data Select = 2 Type E D efault Value 00h D escription This value is mapped to the Data field of register 44h when Data Select (also in register 44h) is set to 2. B it 19:18 Data Scale for Data Select = 1 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 1. Preliminary Data Sheet 140 01.00 PSB 4610 Power Managem ent Configuration Space Register: 48h (cont'd) B it 17:10 Data for Data Select = 1 Type E D efault Value 00h D escription This value is mapped to the Data field of register 44h when Data Select (also in register 44h) is set to 1. B it 9:8 Data Scale for Data Select = 0 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 0. B it 7:0 Data for Data Select = 0 Type E D efault Value 00h D escription This value is mapped to the Data field of register 44h when Data Select (also in register 44h) is set to 0. ________________________________________ Preliminary Data Sheet 141 01.00 PSB 4610 Power Managem ent ________________________________________ Configuration Space Register: 4Ch B it 31:30 Reserved Type H Value 00h B it 29:28 Data Scale for Data Select = 5 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 5. B it 27:20 Data for Data Select = 5 Type E D efault Value 00h D escription This value is mapped to the Data field of register 40h when Data Select (also in register 44h) is set to 5. B it 19:18 Data Scale for Data Select = 4 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 4. Preliminary Data Sheet 142 01.00 PSB 4610 Power Managem ent Configuration Space Register: 4Ch (cont'd) B it 17:10 Data for Data Select = 4 Type E D efault Value 00h D escription This value is mapped to the Data field of register 44h when Data Select (also in register 44h) is set to 4. B it 9:8 Data Scale for Data Select = 3 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 3. B it 7:0 Data for Data Select = 3 Type E D efault Value 00h D escription This value is mapped to the Data field of register 44h when Data Select (also in register 44h) is set to 3. ________________________________________ Preliminary Data Sheet 143 01.00 PSB 4610 Power Managem ent ________________________________________ Configuration Space Register: 50h B it 31:20 Reserved Type H Value 00b B it 19:18 Data Scale for Data Select = 7 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 7. B it 17:10 Data for Data Select = 7 Type E D efault Value 00h D escription This value is mapped to the Data field of register 44h when Data Select (also in register 44h) is set to 7. B it 9:8 Data Scale for Data Select = 6 Type E D efault Value 00b D escription This value is mapped to the Data Scale field of register 44h when D ata Select (also in register 44h) is set to 6. Preliminary Data Sheet 144 01.00 PSB 4610 Power Managem ent Configuration Space Register: 50h (cont'd) B it 7:0 Data for Data Select = 6 Type E D efault Value 00h D escription This value is mapped to the Data field of register 44h when Data Select (also in register 44h) is set to 6. ________________________________________ Preliminary Data Sheet 145 01.00 PSB 4610 Power Managem ent 6.1.4 Electrical Characteristics ________________________________________ Vaux Power Supply in different Power Management Modes State Typ Max D0 19 mA D1 19 mA D2 19 mA D3hot 19 mA D3cold 19 mA ________________________________________ Description of the Table The table above shows the current drawn by the Vaux power supply in different power management modes. The PITA-2 meets the 20mA limit defined for D3cold disabled PCI slots. ________________________________________ Preliminary Data Sheet 146 01.00 PSB 4610 Power Managem ent 6.1.5 Design Hints ________________________________________ D3cold For a design that supports D3cold it is important to check all signals on the local bus side of the PITA-2 that may be affected by a missing Vdd3. As during D3cold Vdd3 w ill drop to zero all pins that are strapped to Vdd3 either directly or by a pullup will also drop to zero. Therefore it is strongly recommended to strap pins on the local bus side of the PITA-2 to Vaux instead. This is especially important for the test pin (pin 1) of the PITA-2. If this pin is not kept at a high level during D3cold the PITA-2 will not be able to reliably assert PME#. Pins that can cause an interrupt (INT0 and GP0-GP3) should also be checked to avoid unwanted PME# events. ________________________________________ Preliminary Data Sheet 147 01.00 PSB 4610 Power Managem ent 6.1.6 Compatibility Issues ________________________________________ Supported Designs by PITA The PITA-2 supports designs which are compliant to the PCI Local Bus Specification R evision 2.2 and the PCI Bus Power Management Interface Specification Revision 1.1. ________________________________________ Potential Compatibility Problem The only potential compatibility problem arises if the PITA-2 is used in a design which: * uses the PME signal * does not support D3cold In this case it may be tempting to connect the Vaux power supply of the PITA-2 directly to the 3.3V signal of the PC I connector and likewise directly connect the PME signal of the PITA-2 to the PME# signal of the PCI connector. However, such a design may affect a PCI system, which: * supports Vaux * has at least one device with D3cold support connected Under these circumstances the following unwanted behavior may happen: The PCI system enters D3cold and the PCI bus enters state B3. In this state the supply pow er 3.3V is disabled while Vaux remains active. As the PITA-2 is connected to the 3.3V supply its own supply Vaux w ill also float. The PME signal of the PITA-2 has an internal clamp diode which will limit the voltage on PME to about Vaux+0.7V. Therefore it is likely that the PITA-2 w ill pull down the PME# signal and therefore block all other D3cold compliant devices on the bus. This behavior can be easily avoided by implementing Vaux detection and power switching as the PITA-2 meets the power supply requirements for PCI slots that do not support D3cold but have Vaux power supply. If the PC I device cannot generate a PME event at all it is best to leave the PME# signal of the PCI connector not connected. ________________________________________ Preliminary Data Sheet 148 01.00 PSB 4610 Reset and Interrupts 7 Reset and Interrupts ________________________________________ 7.1 Reset ________________________________________ Introduction After each power up the PITA-2 must be reset. This reset is necessary to establish a well defined state for all subsequent actions. This chapter informs about: * * * * * reset phases external signals affected by reset internal registers affected by reset pinstrapping automatic reconfiguration ________________________________________ Reset Phases The PITA-2 can be only reset by pulling the RST signal low and then high while the PITA-2 is powered up. There is no provision for a power on reset. Furthermore the PITA-2 requires seven clock cycles after the rising edge of the RST signal. After the rising edge the PITA-2 may start the automatic reconfiguration. D uring this process it copies the contents of an external EEPROM into selected fields of the configuration space registers. Automatic reconfiguration is entered w hen signal ELD is strapped to H. Otherwise the PITA-2 will skip this phase. ________________________________________ Preliminary Data Sheet 149 01.00 PSB 4610 Reset and Interrupts ________________________________________ External Signals All PCI signals are floated as long as the R ST signal is low. Significant input signals (GPIO0-GPIO3, PA0-PA7, PAD0-PAD7 and ELD) must remain stable at least six clock cycles after the rising edge of the RST signal. The signal PRST is forced to low (inactive state) at the rising edge of RST. The signal SRST is forced to high (inactive state) at the rising edge of RST. Usually both signals have not been active before the RST signal has been asserted. Therefore no signal change will usually happen at both SRST and PSRT. As a consequence components which are connected to one of these signals are not automatically reset by a PCI reset. This behavior is desirable when these components remain active during D3cold because after a wake up the SW driver can obtain valuable information from these devices about the reason for a wake up. On the other hand, for a complete initialization of the PCI device the SW driver must perform a reset for these devices by specifically programming the internal registers of the PITA-2. ________________________________________ Internal Registers All internal register fields that are affected by an external reset are marked by a default value in the register description. This default value may be overridden by the optional automatic reconfiguration process. After an external reset the PITA-2 allows only configuration space accesses. Furthermore the PITA-2 will abort configuration space accesses until it has completed the reset sequence (including the optional automatic reconfiguration process). Therefore the SW driver will not be able to read any incorrect transient value from any configuration space register. For the power management the follow ing bits are not affected by an external reset (sticky bits): * configuration space 44h:8 * configuration space 44h:15 * internal register 18h:24-27 The reason for this behavior is that the PITA-2 supports the D3cold state and thus must be able to assert a PME signal even while RST is low. ________________________________________ Preliminary Data Sheet 150 01.00 PSB 4610 Reset and Interrupts ________________________________________ Pinstrapping Pinstrapping is used for: * Loading the Subsystem Vendor ID. * Loading the least significant 4 bits of the Subsystem ID to the PCI Configuration Space. Several output pins from the parallel micro controller interface and the general purpose I/O interface are implemented as tristate output pins. During PCI reset they are driven in tristate mode and the external logic value is latched in the Subsystem ID (4 LSBs) and the Subsystem Vendor ID. This means that the signals on board, connected to these pins, must be forced with pullup/ pulldown resistors to the desired value if they are not driven by the PITA-2. Signal Name Usage during PCI Reset (pinstrapping) PAD(7:0) Subsystem Vendor ID(15:8) PA(7:0) Subsystem Vendor ID(7:0) GP3 Subsystem ID(3) GP2 Subsystem ID(2) GP1 Subsystem ID(1) GP0 Subsystem ID(0) ________________________________________ Automatic reconfiguration of the PITA-2 with the serial EEPROM The PITA-2 can also be configured by the EEPROM after system reset. Pinstrap values are overwritten by this process if the procedure described in "Automatic reconfiguration of the PITA" on page 116 was successful. The PITA-2 w ill reconfiguration. abort PCI configuration accesses during automatic ________________________________________ Preliminary Data Sheet 151 01.00 PSB 4610 Reset and Interrupts 7.2 Interrupts ________________________________________ Introduction The PITA-2 can generate an interrupt on the PCI signal INTA * external, asynchronous event (e.g. an incoming call) * internal, synchronous event (e.g. an EEPROM access finished)) ________________________________________ General Notes The PITA-2 can only assert IN TA if the following requirements are met: * PITA-2 is in D0 or D1 state * the interrupt source is enabled by setting the corresponding interrupt enable bit in internal register 00h (ICR). * the event has occurred Once INTA has been asserted by the PITA-2 it will stay active until a write transaction to the internal register ICR occurs. After this write transaction has occurred the PITA-2 deasserts the signal INTA. The PITA-2 will immediately after this write transaction assert INTA again if either of the following conditions holds: * not all interrupt reporting bits have been cleared * the requirements for asserting an interrupt still hold The former condition usually arises when more than one source has been activated and the interrupt handler reacts to the events sequentially. The latter condition usually arises if an external event has occurred a second time while the interrupt handler is still processing the first occurrence of this event. Reporting bits w ithin the internal register IC R can only be cleared by w riting a logical 1 at the bits that shall be cleared. A read access to this register does not clear any bit nor does it affect any signal. ________________________________________ Preliminary Data Sheet 152 01.00 PSB 4610 Reset and Interrupts ________________________________________ External Events For external events either the dedicated INT0 pin or one of the General Purpose IO pins (GP0-GP3) can be used. The following table shows how to program the PITA-2 in order to activate one or more of these pins for interrupts. ________________________________________ Programming of the PITA-2 Source Enabled by Reported by Active Level INT0 00h:INT0_EN=1 00h:INT0_POL=1 00h:INT0=1 H INT0 00h:INT0_EN=1 00h:INT0_POL=0 00h:INT0=1 L GP0 00h:GP0_INT=1 18h:GP0_INT_EN = 1 18h:GP0_OUT_EN = 0 00h:GP0_INT=1 L GP1 00h:GP1_INT=1 18h:GP1_INT_EN = 1 18h:GP1_OUT_EN = 0 00h:GP1_INT=1 L GP2 00h:GP2_INT=1 18h:GP2_INT_EN = 1 18h:GP2_OUT_EN = 0 00h:GP2_INT=1 L GP3 00h:GP3_INT=1 18h:GP3_INT_EN = 1 18h:GP3_OUT_EN = 0 00h:GP3_INT=1 L ________________________________________ Preliminary Data Sheet 153 01.00 PSB 4610 Reset and Interrupts ________________________________________ Internal Events The following internal events can trigger an interrupt when enabled: * * * * * an EEPROM command has finished the programmed number of writes to the DMA buffer has occurred FIFO overflow (receive failure) FIFO underflow (transmit failure) the PCI retry counter has expired (too many retries for a single transfer) ________________________________________ Summation of the used Bits in Register ICR Event Enabled by Reported by EEPROM command finished 00h:28=1 00h:12=1 DMA watermark reached 00h:24=1 00h:8=1 FIFO overflow 00h:25=0 00h:9=1 FIFO underflow 00h:26=1 00h:10=1 PCI retries expired 00h:27=1 00h:11=1 ________________________________________ EEPROM Command finished & DMA Watermark reached The EEPROM command finished and the DMA watermark reached interrupts are normal events. ________________________________________ FIFO Overflow & FIFO Underflow The FIFO overflow and FIFO underflow events indicate a fatal error w hich may result in a communication failure. The actual impact of these events depends on the error detection and error correction capabilities of the communication protocol of the application. ________________________________________ Preliminary Data Sheet 154 01.00 PSB 4610 Reset and Interrupts ________________________________________ PCI Retries expired The PCI retries expired event is not a normal event but is not necessarily a fatal event. If the PITA-2 reports this event the following has happened: * * * * The DMA controller has requested a data word transfer to/from the FIFO. The PITA-2 has requested the PC I bus for the transfer. The PITA-2 has been granted the PCI bus. The PITA-2 has initiated the transfer <n> times but the PCI target has aborted the transfer each time. <n> is the number programmed in internal register 1Ch:23:16. At this point the PITA-2 releases the PCI bus and reports the event. However, as the DMA data transfer request is not satisfied the PITA-2 will request the PCI bus again for the same data transfer until the request is satisfied. D epending on the PC I target this may either have no effect (data delivered in time finally) or a fatal event may happen (FIFO overflow/underflow). ________________________________________ Caution It is important to bear in mind that in D3cold state Vdd3 will vanish. For devices that support D3cold it is therefore strongly recommended to strap low active interrupt sources (e.g. GP0-GP3) not to Vdd3 but to Vaux instead. ________________________________________ Preliminary Data Sheet 155 01.00 PSB 4610 Pinning 8 Pinning ________________________________________ PITA-2 Pinout VSS VIO VDD3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 C/B E0 AD8 61 60 59 58 57 56 55 54 53 52 51 67 62 CS1 68 INTA PA7 69 63 PA6 70 64 PA5 71 CS2 PA4 72 PA0 PA3 73 65 PA2 74 66 VAUX PA1 75 This illustration shows the numbered pins and their respective signals: PRST 76 50 AD9 PAD7 77 49 AD1 0 PAD6 78 48 AD1 1 PAD5 79 47 AD1 2 PAD4 80 46 AD1 3 PAD3 81 45 AD1 4 PAD2 82 44 AD15 PAD1 83 43 C/ BE1 PAD0 84 42 PAR RD 85 41 SERR WR 86 40 PERR CS0 87 39 STOP VAUX 88 38 DEVSEL VSS 89 37 TRDY PM E_EN 90 36 IRDY ALE 91 35 FRAME INT0 92 34 C/ BE2 SRST 93 33 AD1 6 DCL 94 32 AD1 7 RXD 95 31 AD1 8 TXD 96 30 AD1 9 FSC 97 29 AD2 0 VAUX_PR 98 28 AD2 1 ELD 99 27 AD2 2 ECS 100 26 AD2 3 21 22 AD26 AD25 25 20 AD27 IDSEL 19 AD28 24 18 AD29 23 17 AD30 AD24 16 C/BE3 15 10 GNT AD31 9 CLK VDD3 8 RS T 14 7 PME VIO 6 13 5 GP0 V AUX 12 4 GP1 CL KRUN VSS 3 GP2 11 2 GP3 REQ 1 TES T PITA-2 T-QFP-100-10 ________________________________________ Preliminary Data Sheet 156 01.00 PSB 4610 Pinning ________________________________________ Overview The following table lists the interfaces and their respective pins: Interface Total In Out I/O Page PCI bus 52 4 5 43 158 Parallel Interface 23 3 14 8 159 Serial Interface 5 2 2 1 161 GP I/O Interface 4 0 0 4 162 Special EEPROM Signals 2 1 1 0 163 Power Management 2 1 1 ________________________________________ Description of PIN Types Type Description O/PS Output Pin/Pin Strap Pin I Input Pin IO Bidirectional Input/Output Pin OD Open Drain ________________________________________ Preliminary Data Sheet 157 01.00 PSB 4610 Pinning ________________________________________ This table lists the Pins Characteristics of the PCI Bus Pin No. Signal Name Pin Count Type Function 9 CLK 1 I PC I - Clock (max. 33 MHz) 8 RST 1 I PC I - Reset 16 - 23, 26 - 33, 44 - 51, 53 - 60 AD(31:0) 32 IO PC I - Address-/Data bus 24, 34, 43, 52 C /BE(3:0) 4 IO PC I - Command/Byte Enable Bus (Byte Enables are low active) 42 PAR 1 IO PC I - Parity 64 INTA 1 OD PC I - Interrupt Signal 25 IDSEL 1 I PC I - Initialization Device Select Signal For CardBus boards this signal must set to `1' 35 FRAME 1 IO PC I - Frame 36 IRDY 1 IO PC I - Initiator Ready 37 TRDY 1 IO PC I -Target Ready 38 DEVSEL 1 IO PC I - Device Select 39 STOP 1 IO PC I - Stop 11 R EQ 1 OTS 10 GNT 1 I Preliminary Data Sheet 158 PC I - Bus Request PC I - Bus Grant 01.00 PSB 4610 Pinning This table lists the Pins Characteristics of the PCI Bus (cont'd) Pin No. Signal Name Pin Count Type Function 40 PERR 1 IO PC I - Parity Error 41 SERR 1 OD PC I - System Error 7 PME 1 OD PC I - Power Management Event 12 CLKRUN 1 I Clock Run ________________________________________ This table lists the Pins Characteristics of the Parallel Interfaces Pin No. Signal Name Pin Count Type Function 76 PRST 1 O Active high reset 66, 67, 87 CS(2:0) 3 O Chip Select Signals for three devices connected to the parallel micro controller interface. 84 - 77 PAD(7:0) 8 IO - Multiplexed Bus Mode: Address/Data bus for the parallel interface. - Non-Multiplexed Bus Mode: Data bus for the parallel interface. Preliminary Data Sheet 159 01.00 PSB 4610 Pinning This table lists the Pins Characteristics of the Parallel Interfaces (cont'd) Pin No. Signal Name Pin Count Type Function 74 - 68, 65 PA(7:0) 8 O/PS - Multiplexed Bus Mode: Not used; pins can be left not connected. - Non-Multiplexed Bus Mode: Address bus for the parallel interface. 91 ALE 1 O Address Latch Enable Signal, active high. In non-multiplexed mode the ALE input of peripheral devices must be connected to VSS. 86 WR 1 O Write Signal, active low 85 RD 1 O Read Signal, active low 92 INT0 1 I Standard active low interrupt input for connected devices, which is forwarded to the PC I interface (INTA). ________________________________________ Preliminary Data Sheet 160 01.00 PSB 4610 Pinning ________________________________________ This table list the Pins Characteristics of the Serial Interface Pin No. Signal Name Pin Count Type Function 93 SRST 1 O Active low reset output. 97 FSC 1 I Frame Synchronization Clock signal, 8 kH z. 94 DCL 1 I O (OD) Serial Data Clock Signal. The direction of this pin can be controlled by the DCL_Out_En bit in the internal registers. By default this pin is input. For PSB4596 V2.1 mode, this pin must configured as output (open drain), for all other modes this pin must be input. 95 RXD 1 I Serial Data Input Signal 96 TXD 1 O (OD) Serial Data Output Signal ________________________________________ Preliminary Data Sheet 161 01.00 PSB 4610 Pinning ________________________________________ This table lists the Pins Characteristics of the General Purpose I/O Interface Pin No. Signal Name Pin Count Type Function 2 GP3 1 IO General Purpose I/O Pin 3 This pin is driven high during the automatic EEPROM configuration if ELD = `1'. 3 GP2 1 IO General Purpose I/O Pin 2 Serial EEPROM Interface: SCK - Serial Clock Signal. 4 GP1 1 IO General Purpose I/O Pin 1 Serial EEPROM Interface: SO - Serial Data Output from EEPROM (input to the PITA-2). 5 GP0 1 IO General Purpose I/O Pin 0 Serial EEPROM Interface: SI - Serial Data Input to the EEPROM (output from the PITA-2). ________________________________________ Preliminary Data Sheet 162 01.00 PSB 4610 Pinning ________________________________________ This table lists the Pins Characteristics of the Special EEPROM Signals Pin No. Signal Name Pin Count Type Function 99 ELD 1 I EEPROM Load '1' -> EEPROM Configuration is enabled. '0' -> EEPROM Configuration is disabled. 100 ECS 1 O EEPROM Chip Select (SPI Signal) ________________________________________ Preliminary Data Sheet 163 01.00 PSB 4610 Pinning ________________________________________ This table lists the Pins Characteristics of the Power Management Pin No. Signal Name Pin Count Type Function 90 PME_EN 1 O Reflects the state of the PME_EN bit. Can be used to power down all external logic that is not needed in state D3. 98 VAUX_PR 1 I Indicates that Vaux is present. Preliminary Data Sheet 164 01.00 PSB 4610 Pinning ________________________________________ This table lists the Pins Characteristics of the Power Supply Pin No. Signal Name Pin Count Type Function 15, 61 VDD3 5 I Positive Power Supply 3.3V 10% 6, 75, 88 Vaux 3 I Positive Power Supply 3.3V 10% 14, 62 VIO 2 I IO Voltage Supply (either 3.3V or 5V) 13, 63, 89 VSS 3 I Ground 0V ________________________________________ Preliminary Data Sheet 165 01.00 PSB 4610 Electrical Characteristics 9 Electrical Characteristics ________________________________________ Overview: Overview Page Absolute Maximum Ratings 167 D C Characteristics 168 ________________________________________ Pin Groups The PITA-2 has two different kind of pins: * PC I Pins (8-12, 16-60 and 64) These pins are pow ered by VDD3 and VIO and are intended for connection to the PCI bus. * Local Pins (1-5, 7, 65-74, 76-87 and 90-100) These pins are powered by VAUX or VDD3 (one pow er supply is sufficient) and are intended for connection to the local signal of the PCI device. The AC and D C specification for these two groups are may be different and are therefore listed in separate tables for each group. ________________________________________ Preliminary Data Sheet 166 01.00 PSB 4610 Electrical Characteristics 9.1 Absolute Maximum Ratings ________________________________________ This Table shows the Parameters for the Absolute Maximum Ratings Parameter Limit Values Unit Voltage on PC I pins w ith respect to ground VS1 - 0.5 to V IO + 0.5 V Voltage on local pins w ith respect to ground VS2 - 0.3 to 5.5 V Ambient temperature under bias TA 0 to 70 C Storage temperature T stg - 65 to 150 C Maximum voltage on VIO VDD 7 V Maximum voltage on VDD 3 and VAUX VDD 4.6 V ________________________________________ Note: Stresses above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. Exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. This is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. ________________________________________ Preliminary Data Sheet 167 01.00 PSB 4610 Electrical Characteristics 9.2 DC Characteristics ________________________________________ Description The DC characteristics of the PITA-2 are given in three separate tables: * PC I pins, 5V signaling environment (VIO = 5V) * PC I pins, 3.3V signaling environment (VIO = 3.3V) * Local pins ________________________________________ Conditions 5V Signaling Environment TA = 0 to 70 C; VIO = 4.75V to 5.25V, V aux and VDD3 = 3.0V to 3.6V, V SS = 0 V 3.3V Signaling Environm ent TA = 0 to 70 C; VIO, Vaux and V DD3 = 3.0V to 3.6V, VSS = 0 V ________________________________________ Preliminary Data Sheet 168 01.00 PSB 4610 Electrical Characteristics ________________________________________ DC Characteristics PCI Pins (5V Signaling Environment) Parameter Sym Limit Values min max Unit Test C ondition Rem. Input High Voltage VIH 2.0 V IO+ 0.5 V Input Low Voltage VIL -0.5 0.8 V Input High Leakage Current IIH 70 uA Vin = 2.7V 1) Input Low Leakage Current IIL -70 uA Vin = 0.5V 2) V IOH = -2mA IOL = 3/6 mA Output H igh Voltage VOH L-output voltage VOL 0.55 V Input Pin Capacitance CIN 10 if 1) 2) 3) 2.4 Pin Inductance LPIN 20 nH PME# Input Leakage IOFF 1 uA 3) Vout below 5.25V VD D3 off/floating exce pt fo r CLK RUN which i s in te rn ally pu lle d do wn (I LIh = 50 0 uA exce pt fo r CLK RUN which i s in te rn ally pu lle d do wn (I LIh = 50 0 uA 6m A for FRA ME, TRDY , IR DY, DEV SE L , STO P , SE RR , P ERR, LO CK a nd INTA ________________________________________ Preliminary Data Sheet 169 01.00 PSB 4610 Electrical Characteristics ________________________________________ DC Characteristics PCI Pins (3.3V Signaling Environment) Parameter Sym Limit Values min max Unit Test Condition Rem. uA 0 < Vin < VIO 1) V IOH = -0.5 mA IOL = 1.5mA Input High Voltage VIH 0.5V IO V IO+ 0.5 V Input Low Voltage VIL -0.5 0.3V IO V Input Leakage Current I IL -10 10 Output H igh Voltage VOH L-output voltage VOL 0.1V IO V Input Pin Capacitance CIN 10 pF 1) 0.9V IO Pin Inductance LPIN 20 nH PME# Input Leakage I OFF 1 uA Vout below 3.6V VDD3 off/ floating exce pt fo r CLK RUN which i s in te rn ally pu lle d do wn (I LIh = 50 0 uA ________________________________________ Preliminary Data Sheet 170 01.00 PSB 4610 Electrical Characteristics ________________________________________ DC Characteristics Local Pins Parameter Sym Limit Values min max Unit Input High Voltage VIH 2.4 5.25 V Input Low Voltage VIL -0.3 0.8 V Input Leakage Current I IL -10 10 uA Output H igh Voltage VOH L-output voltage VOL 2.4 0.4 Test Condition V IOH = -2 mA V IOL = 2 mA Rem. ________________________________________ Preliminary Data Sheet 171 01.00 PSB 4610 Package Outlines 10 Package Outlines Preliminary Data Sheet 172 01.00 PSB 4610 Configuration Space Register of the PITA-2 11 Configuration Space Register of the PITA-2 ________________________________________ Overview Page D escription of the Register Types 174 C onfiguration Space Registers 175 R egisters which do not occur elsew here in the Data Sheet 185 ________________________________________ Preliminary Data Sheet 173 01.00 PSB 4610 Configuration Space Register of the PITA-2 11.1 Description of the Register Types ________________________________________ Description of the Register Types Type Description PE H * read only via PC I * these bits are initialized by pinstrapping during PCI reset or by the optional EEPR OM * read only via PC I * hardwired RC * read clear via PCI * these bits are set by the internal logic * these bits can be read out and reset by writing logical "1" to them * writing logical "0" doesn't influence the states of these bits RW * read write via PCI * these bits can be read out and written via the PCI bus E * read only via PC I * these bits are initialized to a default value during PCI reset or by the optional EEPROM ________________________________________ Preliminary Data Sheet 174 01.00 PSB 4610 Configuration Space Register of the PITA-2 11.2 Configuration Space Registers ________________________________________ 00h A d. Bit Type Default Value Register Name Page 00h 31:16 E 2104h Device ID 185 15:0 E 110Ah Vendor ID of Siemens AG. 185 ________________________________________ 04h A d. Bit 04h 31:0 Type Default Value Register Name Page 0290 0000h PCI Status Register 185 31 RC 0b Parity Error D etected 185 30 RC 0b System Error Signaled 90 29 RC 0b Master Abort Detected 90 28 RC 0b Target Abort Detected 90 27 RC 0b Target Abort Signaled 90 26:25 H 01b DEVSEL Timing 26 28 24 RC 0b Data Parity Error Reported 185 23 H 1b Fast Back-to-Back Capability 30 22 H 0b User Defined Functions 185 21 H 0b 66 MHz Capability 185 Preliminary Data Sheet 175 01.00 PSB 4610 Configuration Space Register of the PITA-2 04h (cont'd) A d. Bit Type Default Value Register Name 20 E 1b Capabilities 185 19:16 H 0000b Reserved 185 Command Register 185 15:0 Page 15:10 H 000000b Reserved 185 9 H 0b Fast Back-to-Back Enable 30 8 RW 0b System Error Enable 90 7 H 0b Address/Data Stepping Enable (not used) 185 6 RW 0b Parity Error R esponse 185 5:3 H 000b The PITA-2 does not support the Special Cycle Command. 185 2 RW 0b Master Enable 90 1 RW 0b Memory Access Enable 17 0 H 0b I/O Access Enable 185 ________________________________________ 08h A d. Bit Type Default Value Register Name 08h 31:8 E 028000h Class Code/PCI network device 188 7:0 E 02h Revision ID 188 Preliminary Data Sheet 176 Page 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 0Ch A d. Bit Type Default Value Register Name Page 0C h 31:24 H 00h BIST 189 23:16 H 00h Header Type 189 15:8 H 00h Master Latency Timer 189 7:0 H 00h Cache Line Size 189 ________________________________________ 10h A d. Bit 10h 31:0 31:12 11:0 Type Default Value Register Name Page 00000000h Base Register 0 17 RW H ________________________________________ 14h A d. Bit 14h 31:0 31:12 11:0 Type Default Value Register Name Page 00000000h Base Register 1 18 RW H ________________________________________ Preliminary Data Sheet 177 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 18h A d. Bit Type Default Value Register Name 18h 31:0 H 00000000h Base Address Register 2 (not used) Page 18 ________________________________________ 1Ch A d. Bit Type Default Value Register Name 1C h 31:0 H 00000000h Base Address Register 3 (not used) Page 18 ________________________________________ 20h A d. Bit Type Default Value Register Name 20h 31:0 H 00000000h Base Address Register 4 (not used) Page 19 ________________________________________ 24h A d. Bit Type Default Value Register Name 24h 31:0 H 00000000h Base Address Register 5 (not used) Page 19 ________________________________________ Preliminary Data Sheet 178 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 28h A d. Bit 28h 31:0 Type Default Value Register Name Page 0000 02C0 CardBus CIS Pointer 20 31:28 H 0000b ROM Image Number 20 27:3 H 000054h Address Space Offset 20 2:0 H 000b Address Space Indicator 21 ________________________________________ 2Ch A d. Bit Type Default Value Register Name Page 2C h 31:20 E 000h Subsystem ID 21 19:16 PE pinstrap value or EEPROMvalue 15:0 PE pinstrap value or EEPROMvalue Subsystem Vendor ID 21 ________________________________________ Preliminary Data Sheet 179 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 30h A d. Bit Type Default Value Register Name 30h 31:0 H 00000000h Reserved Page 190 ________________________________________ 34h A d. Bit Type Default Value Register Name Page 34h 31:8 H 00h Reserved 132 7:0 H 40h Capabilities Pointer 132 ________________________________________ 38h A d. Bit Type Default Value Register Name 38h 31:0 H 00000000h Reserved Page 190 ________________________________________ 3Ch A d. Bit Type Default Value Register Name 3C h 31:24 E 00h Max_Lat 191 23:16 E 00h Min_Gnt 191 15:8 H 01h Interrupt pin 191 Preliminary Data Sheet 180 Page 01.00 PSB 4610 Configuration Space Register of the PITA-2 3Ch (cont'd) A d. Bit Type Default Value Register Name 7:0 RW FFh Interrupt Line Page 191 ________________________________________ 40h A d. Bit 40h 31:0 Type Default Value Register Name Page 1222 0001 Power Management Capabilities (PMC) 133 PME_Support 133 31:30 E 00b 29:28 E 01b 27 E 0b 26 E 0b D2_Support 133 25 E 1b D1_Support 133 24:22 E 000b Aux Current 133 21 E 1b DSI 133 20 H 0b Reserved 133 19 E 0b PME Clock 133 18:16 E 010b Version The value 010b indicates that the device complies with the Revision 1.1 of the PCI Power Management Interface Specification. 133 15:8 H 00h Next Item Ptr 133 7:0 H 01h Capability ID 133 Preliminary Data Sheet 181 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 44h A d. Bit Type Default Value Register Name Page 44h 31:24 H 00h DATA Register 137 23:16 H 00h PMCSR_BSE Bridge Support Extensions 137 15 RC 0b PME Status 137 14:13 H 00b Data Scale 137 12:9 RW 0h Data Select 137 8 RW 0b PME_En 137 7:2 H 00h Reserved 137 1:0 RW 00b Power State 137 ________________________________________ 48h A d. Bit 48h 31:0 Type Default Value Register Name1 Page Power Data Register 1 140 31:30 H 00b Reserved 140 29:28 H/EW 00b Data_Scale in Data_Select = 2 140 27:20 H/EW 00h DATA in Data_Select = 2 140 19:18 H/EW 00b Data_Scale in Data_Select = 1 140 17:10 H/EW 00h DATA in Data_Select = 1 140 Preliminary Data Sheet 182 01.00 PSB 4610 Configuration Space Register of the PITA-2 48h (cont'd) A d. Bit Type Default Value Register Name1 Page 9:8 H/EW 00b Data_Scale in Data_Select = 0 140 7:0 H/EW 00h DATA in Data_Select = 0 140 ________________________________________ 4Ch A d. Bit 4C h 31:0 Type Default Value Register Name Page Power Data Register 2 142 31:30 H 00b Reserved 142 29:28 E 00b Data_Scale in Data_Select = 5 142 27:20 E 00h DATA in Data_Select = 5 142 19:18 E 00b Data_Scale in Data_Select = 4 142 17:10 E 00h DATA in Data_Select = 4 142 9:8 E 00b Data_Scale in Data_Select = 3 142 7:0 E 00h DATA in Data_Select = 3 142 ________________________________________ Preliminary Data Sheet 183 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 50h A d. Bit 50h 31:0 Type Default Value Register Name Page Power Data Register 3 144 31:20 H 000h Reserved 144 19:18 E 00b Data_Scale in Data_Select = 7 144 17:10 E 00h Data_Value in Data_Select = 7 144 9:8 E 00b Data_Scale in Data_Select = 6 144 7:0 E 00h Data_Value in Data_Select = 6 144 ________________________________________ 54h A d. Bit Type Default Value Register Name Page 54h 31:0 H 00h CardBus CIS 192 ________________________________________ Preliminary Data Sheet 184 01.00 PSB 4610 Configuration Space Register of the PITA-2 11.3 Registers which do not occur elsewhere in the Data Sheet ________________________________________ 00h B it 31:16 Device ID Type E D efault Value 2104h D escription Identifies the PITA-2 within all PC I devices from Siemens Semiconductors. B it 15:0 Vendor ID Type E D efault Value 110Ah D escription 110A is the Vendor ID of Siemens AG. ________________________________________ 04h B it 31:0 PCI Status Register D efault Value 02900000h B it 31 Parity_Error_Detected Type RC D efault Value 0b D escription This bit is set, if a parity error is detected during a transaction with the PITA-2. This is done independently from the status of the `Parity Error Response' bit. Preliminary Data Sheet 185 01.00 PSB 4610 Configuration Space Register of the PITA-2 04h (cont'd) B it 24 Data_Parity_Error_Reported Type RC D efault Value 0b D escription The PCI Master asserts this bit if it detects the PERR signal on the PCI bus asserted during a PCI transaction initiated by itself. B it 22 User_D efined_Functions Type H Value 0b D escription The PITA-2 has no user defined functions. B it 21 66_MHz_Capability Type H Value 0b D escription The PITA-2 is not a 66 MHz device (0 - 33 MHz supported.) B it 20 Capabilities Type E D efault Value 1b D escription If this bit is set, the PCI device has additional capabilities defined in the PCI Configuration Space Header. Additional capabilities can be found in the Cap_Ptr under address 34h. Preliminary Data Sheet 186 01.00 PSB 4610 Configuration Space Register of the PITA-2 04h (cont'd) B it 19:16 Reserved Type H D efault Value 0000b D escription B it 15:0 Command Register B it 15:10 Reserved Type H D efault Value 000000b D escription B it 7 Address/Data_Stepping_Enable Type H D efault Value 0b D escription not used B it 6 Parity_Error_Response Type RW D efault Value 0b D escription If this bit is set to `1', the PCI interface reports data parity errors by asserting the PERR signal. Preliminary Data Sheet 187 01.00 PSB 4610 Configuration Space Register of the PITA-2 04h (cont'd) B it 5:3 Type H Value 000b D escription The PITA-2 does not support the Special Cycle Command. The PITA-2 does not generate Memory Write and invalidate transactions. The PITA-2 does not support VGA Palette snooping. B it 0 I/O_Access_Enable Type H D efault Value 0b D escription The PC I interface does not support I/O commands. ________________________________________ 08h B it 31:8 Class_Code Type H or EW D efault Value 028 000h D escription PCI network device B it 7:0 Revision ID Type H D efault Value 02h D escription Revision of the PCI device ________________________________________ Preliminary Data Sheet 188 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 0Ch B it 31:24 BIST Type H D efault Value 00h D escription The PITA-2 has no built-in self test. B it 23:16 Header_Type Type H D efault Value 00h D escription B it 15:8 Master_Latency_Timer Type H D efault Value 00h D escription Unused B it 7:0 Cache_Line_Size Type H D efault Value 00h D escription The PITA-2 does not support the cache line size register because it supports only single data transactions. ________________________________________ Preliminary Data Sheet 189 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 30h B it 31:0 Reserved Type H D efault Value 0000 0000h D escription Reserved ________________________________________ 38h B it 31:0 Reserved Type H D efault Value 0000 0000h D escription ________________________________________ Preliminary Data Sheet 190 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 3Ch B it 31:24 Max_Lat Type E D efault Value 00h D escription Set to '0' because only single data transactions are supported. B it 23:16 Mint_Gnt Type E D efault Value 00h D escription Set to '0' because only single data transactions are supported. B it 15:8 Interrupt_Pin Type H D efault Value 01h D escription As a single function device, the PITA-2 uses the INTA signal. B it 7:0 Interrupt_Line Type RW D efault Value FFh D escription These Bits show the interrupt line which is used by this system. For a x86 system the value FF means unknown. These registers are written during the initialization of the operating system. ________________________________________ Preliminary Data Sheet 191 01.00 PSB 4610 Configuration Space Register of the PITA-2 ________________________________________ 54h B it 31:0 Cardbus_CIS Type H Value 00h D escription Not supported by PITA-2 ________________________________________ Preliminary Data Sheet 192 01.00 PSB 4610 Internal Register of the PITA 12 Internal Register of the PITA ________________________________________ Overview Page D escription of the Register Types 194 Internal Register 195 R egisters w hich do not occur elsewhere in the Data Sheet 202 ________________________________________ Preliminary Data Sheet 193 01.00 PSB 4610 Internal Register of the PITA 12.1 Description of the Register Types ________________________________________ Description of the Register Types Type Description R read only RC read clear * these bits are set by the internal logic * these bits can be read out and reset by writing logical "1" to them * writing logical "0" doesn't influence the states of these bits RW read write * these bits can be read out and written via the PCI bus ________________________________________ Preliminary Data Sheet 194 01.00 PSB 4610 Internal Register of the PITA 12.2 Internal Register ________________________________________ 00h A d. Bit 00h 31:0 Type Default Value Register Name Page 00000000h ICR - Interrupt Control Register 202 31:29 R 000b Reserved 202 28 RW 0b EEPROM_Control_Int_En 121 27 RW 0b Retry_Counter_Down_ Int_En 31 26 RW 0b FIFO_Overflow_Empty_ Int_En 41 25 RW 0b DMA_Write_Counter_ Overflow_Int_En 41 24 RW 0b DMA_Write_Counter_Int_ En 41 23:18 R 000000b Reserved 202 17 RW 0b INT0_En 202 16 RW 0b INT0_Pol 202 15:13 R 000b Reserved 202 12 RC 0b EEPROM_Control_Int 121 11 RC 0b Retry_Counter_Int 31 10 RC 0b FIFO_Overflow_Empty_ Int 41 9 RC 0b DMA_Write_Counter_ Overflow_Int 41 8 RC 0b DMA_Write_Counter_Int 41 Preliminary Data Sheet 195 01.00 PSB 4610 Internal Register of the PITA 00h (cont'd) A d. Bit Type Default Value Register Name Page 7:6 R 0b Reserved 202 5 RC 0b GP3_INT 101 4 RC 0b GP2_INT 101 3 RC 0b GP1_INT 101 2 RC 0b GP0_INT 101 1 RC 0b INT0 202 ________________________________________ 04h A d. Bit 04h 31:0 Type Default Value Register Name Page 00000000h DMA Control Register 43 31:09 R 0000000h Reserved 43 8 RW 0b DMA Start 43 7:6 R 00b Reserved 43 5:0 RW 000000b DMA Select - all modes IOM-2 Mode 1 IOM-2 Mode 2 IOM-2 Mode 3 Single Modem Mode V2.1 Single Modem Mode V3.X Dual Modem+Voice Mode 43 48 52 55 63 67 75 ________________________________________ Preliminary Data Sheet 196 01.00 PSB 4610 Internal Register of the PITA ________________________________________ 08h A d. Bit Type Default Value Register Name 08h 31:12 RW 00000h Circular Buffer Start Address 11:0 R 000h Page 45 ________________________________________ 0Ch A d. Bit Type Default Value Register Name 0C h 31:00 R 00000000h Actual Circular Buffer Pointer Page 45 ________________________________________ 10h A d. Bit 10h 31:0 Type Default Value Register Name Page 00000000h ALIS Command Register 1 67 31:25 R 00h Reserved 67 24 RW 0b New _ALIS_Command_1 67 23:16 RW 00h ALIS_Received_Data_1 67 15:8 RW 00h ALIS_Command_1 67 7:0 RW 0b ALIS_Transmit_Data_1 67 ________________________________________ Preliminary Data Sheet 197 01.00 PSB 4610 Internal Register of the PITA ________________________________________ 14h A d. Bit 14h 31:0 Type Default Value Register Name Page 00000000h ALIS Command Register 2 70 32:25 R 000h Reserved 70 24 RW 0b New _ALIS_Command_2 70 23:16 RW 00h ALIS_Received_Data_2 70 15:8 RW 00h ALIS_Command_2 70 7:0 RW 00h ALIS_Transmit_Data_2 70 ________________________________________ 18h A d. Bit 18h 31:0 Type Default Value Register Name Page 00000000h GP I/O Interface Control Register 102 31:28 R 0h Reserved 102 27 RW 0b GP3_Int_En 102 26 RW 0b GP2_Int_En 102 25 RW 0b GP1_Int_En 102 24 RW 0b GP0_Int_En 102 23:20 R 0000b Reserved 102 19 RW 0b GP3_Out_En 102 18 RW 0b GP2_Out_En 102 Preliminary Data Sheet 198 01.00 PSB 4610 Internal Register of the PITA 18h (cont'd) A d. Bit Type Default Value Register Name Page 17 RW 0b GP1_Out_En 102 16 RW 0b GP0_Out_En 102 15:12 R 0000b Reserved 102 11 R - GP3_IN 102 10 R - GP2_IN 102 9 R - GP1_IN 102 8 R - GP0_IN 102 7:4 R 0000b Reserved 102 3 RW 0b GP3_OUT 102 2 RW 0b GP2_OUT 102 1 RW 0b GP1_OUT 102 0 RW 0b GP0_OUT 102 ________________________________________ 1Ch A d. Bit 1C h 31:0 Type Default Value Register Name Page 00000000h MISC - Miscellaneous Register 59 31 RW 0b IOM B1 Masking 59 30 RW 0b IOM B2 Masking 59 29 RW 0b IOM MON0/IC1 Masking 59 28 RW 0b IOM D+C/I0+MR+MX / IC2 Masking 59 Preliminary Data Sheet 199 01.00 PSB 4610 Internal Register of the PITA 1Ch (cont'd) A d. Bit Type Default Value Register Name Page 27 RW 1b Serial Interface Buffer Mode 204 26 RW 0b Parallel Interface Mode 78 25 RW 1b Soft reset Serial Interface 204 24 RW 0b Soft reset Parallel Interface 78 23:16 RW 00h Retry Count Register 32 15:12 R 0000b Reserved 204 11:0 RW 0000h DMA Write Count Register 46 ________________________________________ 20h A d. Bit 20h 31:0 Type Default Value Register Name 00000000h Serial Clock Select Register Page 31:2 R 00000000h Reserved 1 RW 0b DC L_Out_En 49 52 55 64 72 0 RW 0b Serial_Clock_Sel 49 52 55 64 72 Preliminary Data Sheet 200 01.00 PSB 4610 Internal Register of the PITA ________________________________________ 24h A d. Bit 24h 31:0 Type Default Value Register Name Page 00000000h EEPROM Control Register 121 31:25 R 0000h Reserved 121 24 RW 0b EEPROM Start 121 23:16 RW 00h EEPROM Command 121 15:8 RW 00h EEPROM Byte Address 121 7:0 RW 00h EEPROM Data 121 ________________________________________ 28h A d. Bit 28h 31:0 Type Default Value Register Name Page 00000000h DMA TEST R egister 204 31:01 R 00000000h Reserved 204 0 RW 0b Loop_Back_Mode 77 ________________________________________ Preliminary Data Sheet 201 01.00 PSB 4610 Internal Register of the PITA 12.3 Registers which do not occur elsewhere in the Data Sheet ________________________________________ 00h B it 31:0 ICR - Interrupt Control Register D efault Value 00000000h D escription The interrupt enable bits for GP3-0 are placed in the GP I/O Interface Control Register. All interrupt enables are high active: Int_En='0' -> corresponding interrupt (bit) is disabled Int_En='1' -> corresponding interrupt (bit) is enables B it 31:29 Reserved Type R Value 000b B it 23:18 Reserved Type R Value 000000b B it 17 INT0_En Type RW D efault Value RW D escription Enable for the INT0 interrupt bit. Preliminary Data Sheet 202 01.00 PSB 4610 Internal Register of the PITA 00h (cont'd) B it 16 INT0_POL Type RW D efault Value 0b D escription Polarity of INT0 active level 0: L-Level 1: H-level B it 23:18 Reserved Type R Value 000000b B it 1 INT0 Type RC D efault Value 0b D escription An interrupt is detected on pin INT0 . B it 0 Reserved Type R Value 0b ________________________________________ Preliminary Data Sheet 203 01.00 PSB 4610 Internal Register of the PITA ________________________________________ 1Ch B it 27 Serial Interface Buffer Mode Type RW Value 1b D escription 0: The TXD pin is configured as PUSH /PU LL output pin. 1: The TXD pin is configured as OPEN DRAIN output pin. B it 25 Soft Reset Serial Interface Type RW D efault Value 1b D escription 0: Activates the low active reset signal SRST to the application. 1: Deactivates the reset signal SRST to the application. Before asserting this bit the DMA_Start bit has to be reset. ________________________________________ 28h B it 31:0 DMA Test Register D efault Value 00000000h B it 31:1 Reserved Type R D efault Value 00000000h ________________________________________ Preliminary Data Sheet 204 01.00 PSB 4610 Abbreviations 13 Abbreviations AC Alternating Current. A/D Analog to digital. ADC Analog to digital converter. ALE Address latch enable. ALIS Analog Line Interface Solution. Chip set consisting of PSB4595 and PSB4596. DC Direct Current. DCL Double Bit Clock. (In this context, only in the IOM-2 modes of the serial interface of the PITA, single bit in all other modes). DMA Direct Memory Access. DD Data Downstream. DU Data Upstream. EEPROM = E 2PROM Electrically erasable programmable read only memory. FIFO RX FIFO TX FIFO First in first out. FSC Frame Sync. I/O In/out. IOM ISD N Oriented Modular. ISD N Integrated Services D igital Netw ork. MSB Most Significant Bit. PITA PCI Interface for Telephony/Data Applications. PCI Peripheral Component Interconnect. RXD Receive D irection. TXD Transmit Direction. Preliminary Data Sheet 205 01.00 PSB 4610 Index 14 Index A Absolute Maximum Ratings 167 ALIS V2.1 Configuration after Reset 63 Connection to the PITA-2 118 ALIS V3.X Configuration after Reset 66 B Base Address Register 16 BAR 0 17 BAR 1 18 Structure of the Address Space 16 C Configuration Space Register Power Management 34h 132 40h 133 44h 137, 140, 142, 144 Reference Table 175 D DC Characteristics 168 DMA Algorithm 38 DMA Controller 36 Dual Modem/Modem+Voice Mode 73 G General Purpose I/O Interface Input Mode 107 Interrupt Mode 111 Output Mode 109 97 I Interfaces General Purpose I/O Interface Parallel Interface 78 Serial DMA Interface 34 SPI EEPR OM Interface 115 Semiconductor Group Internal Register 00h 195 20h 200 24h 201 DMA Controller 00h 41 04h 43, 45, 63, 67, 69, 75 08h 45 0Ch 45, 46, 77, 78, 102 1Ch 46 GP I/O Interface 00h 101 18h 102 Loopback Mode 28h 77 Parallel Interface 1Ch 78 Reference Table 195 Retry Counter 00h 31 1Ch 32 Single Modem Mode V2.1 20h 49, 52, 55, 64, 72 SPI EEPROM Interface 00h 67, 70, 121 24h 121 Interrupt Control Register 31 IOM-2 Mode 1 47 IOM-2 Mode 2 50 IOM-2 Mode 3 53 IOM-2 Modes General Description 56 Masking of IOM-2 Timeslots 58 Selection of IOM-2 Timeslots 56 L 97 Loopback Mode 76 M Multiplexed Mode 206 Preliminary Data Sheet 01.00 PSB 4610 Index Read Transaction Write Transaction 88 87 Non Multiplexed Mode Read Transaction Write Transaction 86 84 ALE after internal Softreset 82 ALE after setting the Parallel Interface Mode Bit 83 ALE after System Reset 81 Burst R ead 25 Burst Write 27 Dual Modem/Modem+Voice Mode 74 Fast Back to Back 29 GP I/O Interface Input Mode 107 Interrupt Mode 111 Output Mode 110 IOM-2 all Modes 56 IOM-2 Mode 1 48 IOM-2 Mode 2 51 IOM-2 Mode 3 54 Loopback Mode 76 Parallel Interface Multiplexed Address 94 Non Mulitplexed Address 95 Read 94 Write 94 Single Modem Mode V2.1 61 Single Modem Mode V3.X 65 SPI EEPROM Interface 119 Transaction Disconnect 89 Transaction Termination 92 N P Parallel Interface 78 PCI Bus Pinning 158 PCI Commands 23 PCI Configuration Space 11 Access to the 15 Construction of 13 PCI Master Controller 23 PCI Target Controller 23 Pinning Description of PIN Types 157 GP I/O Interface 162 Parallel Interfaces 159 Power Supply 164, 165 Serial Interface 161 Special EEPR OM Signals 163 Pinstrapping 151 Power Management 123 Power Management States 126 R Reset V 149 Vendor ID 151 S Serial DMA Interface 34 Single Modem Mode V2.1 61 Configuration after Reset 62 Single Modem Mode V3.X 65 Configuration after Reset 66 SPI EEPROM Interface 115 T Timing 89 Timing Diagram Semiconductor Group 207 Preliminary Data Sheet 01.00